Mtech E&TC student . VHDL,Verilog,system verilog programming languages

CURRICULUM VITAE

RUTUJA P. CHAVAN E-mail: acagfz@r.postjobfree.com

Muktangan Banglow, Dhankawdi, Phone: 091-770-***-****

Pune-411043, Maharashtra (state)

Objective:

To be associated with a progressive organization that provides an opportunity to apply my knowledge and skills, for my growth and the growth of the organization. And to pursue a long term career with a reputable organization by meeting challenging tasks and career oriented growth opportunities.

Technical Expertise :

Programming Skills : VHDL, Verilog, C, MATLAB, Assembly Languages, Shell

Scripting, Perl scripting.

Tools:

FPGA Tools : Xilinx 14.1, EDK, Cadence NC-sim, mentor graphics.

Spice Tools : Ngspice, pspice

Other Tools : MATLAB, Keil, Microcap, Microwind, Express PCB

Devices Handled : Microcontrollers: 8051, ARM, PIC

FPGA Kit-spartan & vertex, Embedded Devices

Operating systems: Linux, Windows7, XP,

Education:

Gate qualified: Gate Score: 385 year: 2013

Gate Score: 355 year- 2011

Examination Year Institute Board / University

Percentage

Class

M.E.

2011-2013 VIT

Pune

Pune 9.21 Distinction

B.E.

2006-2010 VPCOE

Baramati

Pune 66.50% Distinction

H.S.C Feb-2006 T.C.College

Baramati Pune 84.83% Distinction

S.S.C Mar-2004 M.E.S Highschool Baramati Pune 80.00% Distinction

Employment and experience

Teaching Assistant – VIT, Pune. August 2011- August 2013

Responsibilities:

I Instructed labs for the students of electronics and communication engineering at bachelors level. The assigned labs were for Digital integrated circuits, CMOS analog and digital design, mixed signal vlsi design.

Handled different tools Xilinx, mentor graphics, cadence -NCsimulator. Worked on Simulation of digital system design using VHDL/Verilog in ASIC (cadence tools) and FPGA (Xilinx tools) flow.

Projects:

Postgraduate Thesis

Main Project

Title: Optimized Parameter Extraction For Semiconductor Devices

Area: VLSI

Technology: C language, GCC compiler on Linux & ngspice simulator

Description: Design of optimizer using artificial bee colony algorithm and design a single model card for different geometry devices by extracting the MOSFET parameters. Also optimizer is used for solar cell diode modeling. Ngspice simulator is used to test the extracted parameters performance.

Mini Project

Title: Design of 4bit barrel shifter in vlsi using ngspice

Area: VLSI

Technology: Ngspice simulator, microwind.

Description: To design 4 bit barrel shifter we require 2 level design. First level provides 2bit shift and second level provides 1 bit shift. Here we need 2 select lines for each level. For this design we use 8 different 4:1 mux. The respective operations are selected by using the control lines. Same design layout is implemented and compared results with spice results.

Undergraduate project

Title: Design of Pico Blaze Microcontroller using VLSI

Area: VLSI (B.E.)

Technology: VHDL language in Xilinx

Description: Pico Blaze Microcontroller is more powerful controller in comparison to others designed by Xilinx. We have designed this controller using VHDL Language which will perform one instruction per two clock cycles .We got the results on Spartan-3 Kit.

Title: Automatic Drip Irrigation System

Area: Embedded System (T.E.)

Technology: Programming of 8051 and layout design.

Description: In this project, considering all aspects for watering crop, the time period of watering is decided & fed as input & the motor is started & turned off automatically as per the timing provided. This project provides totally atomized & cost effective system for drip irrigation.

Co-curricular Activities:

• Attended work shop on “SEQUEL” a circuit simulator, from Prof. M. B. Patil, IIT Bombay.

• Completed Short Term Training Workshop Covering Advance Technologies in ‘Embedded System’ conducted by PROSYS.

• Participated in Competition like Explitron – Circuit design & debugging held in a National Level Technical Symposium - Verismo.

Extra-curricular Activities:

• Worked for Vanavasi Kalyan Aashram, Maharashtra

• Played Kho-Kho and kabaddi for School’s team at taluka level.

• Winner of different Running competitions held in high-school on the occasion of Annual Sport Days.

• Flute player in School’s band

References:

Prof. A.M. Chopde, Head of Electronics Dept, VIT, Pune, Maharashtra.

Email: acagfz@r.postjobfree.com

Prof. Rajveer Shastri, Head of Electronics Dept, VPCOE,Baramati,Maharashtra

Email: acagfz@r.postjobfree.com

Prof. S. R. Deshpande, Principal of Sinhghad College of diploma,Pune, Maharashtra. Email: acagfz@r.postjobfree.com

Declaration:

I hereby declare that the information furnished above is true to the best of my knowledge.

Place: Rutuja Chavan

Date

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