RESUME

Looking for the ANALOG/RF layout position with having experience in layout

design and two tape out knowledges.

J V VIJAYA KUMAR

mail id: acerk8@r.postjobfree.com

+91-777*******.

CAREER OBJECTIVE

Seeking as a challenging position as a best Layout Engineer in a

leading company where innovation, education and sense of ownership are

valued and encouraged

WORK EXPERIENCE:

Working as RF LAYOUT ENGINEER in SM WIRELESS SOLUTIONS PVT Ltd, NAGPUR

under the SISTER CONCERN OF RFIC SOLUTIONS(USA).

WORK OUTLINE:

VLSI Fundamentals, CMOS Basics, latch up issues, Floor Planning, Placement

and Routing, Analog Layout, matching techniques,Cadence virtuoso tool

editor, deep sub micron technologies issues,tapeout.

SUMMARY:

Hands on 1 YEAR 2 months experience in RF/ANALOG layout design and

verification on cadence virtuoso tool. With having a TOP LAVEL

ROUTING,TAPEOUT knowledge, Good knowledge in matching techniques(Inter

digitization, common centroid), latch up issues, antenna effects, power

management techniques, PCELL creation, deep newll process.

Cadence Tools:

Experience in Custom layout designing of 130 nm,45nm technology using

cadence tools.

. Cadence Virtuoso layout editor-floor planning and routing

. Assura verification-DRC & LVS.

. Technology: TSMC 130nm, 45nm,

Global Foundry 180nm, 130nm,

SMIC 55nm.

REAL TIME LAYOUT PROJECTS:

Project1:

Name: RFIC(TRANSRECEIVER)

Technologie:130nm(global)

Tools: : Virtuoso Layout XL,L Editor, Calliber Verification(DRC,LVS)

Role: To develop layout from schematic, floor plan, power

management, clean DRC and LVS, top level

routing.

Description: Worked as a team member for design and development of a fully-

integrated low power RFCMOS transceiver operating at 915.9 MHz - 929.7 MHz.

The device parameters are compliant to the IEEE 802.15.4g standard. The

chip contains a direct-conversion receiver, a fractional-N PLL, a direct-

conversion transmitter and a TR-switch. Digital baseband signal processing

as well as MAC support are also implemented on the same chip.

Challenges: Meet the matching techniques, provide Dummy's to protect the

critical devices, provide guard rings, and draw the

layout in optimized way, Delivering the project on time, TOP LEVEL ROUTING,

GDS2 CONVERSION.

SOME OF HANDLED BLOCKS:

Block name: POWER AMPLIFIER(PA)

Developed a layout for power

amplifier.

Targeted Technology : GF 130nm.

Role : To develop layout from schematic, floor plan,

power

management, clean DRC and LVS.

Challenges : special Take care on the matching techniques,

provide

a dummies,Shielding Technique, power management, take care on deep sub

micron techniques, provide guard rings, and Draw the layout in optimized

way

Block name: BUFFER

Developed a layout for BUFFER.

Targeted Technology : GF 130nm.

Role : To develop layout from schematic, floor plan,

power

management, clean DRC and LVS.

Challenges: provide guard rings, and Draw the layout in

optimized way.

Block name: ATTENUATOR

Developed a layout for

ATTENUATOR.

Targeted Technology : GF 130nm.

Role : To develop layout from schematic, floor plan,

power

management, clean DRC and LVS.

Challenges: provide guard rings, and Draw the layout in

optimized way.

Block name: LOW PASS FILTER

Developed a layout for LOW PASS

FILTER.

Targeted Technology : GF 130nm.

Role : To develop layout from schematic, floor plan,

power

management, clean DRC and LVS.

Challenges: provide guard rings, and Draw the layout in

optimized way.

PROJECT2:

Name: FEM(Front End Module)

Technologie:55nm(SMIC)

Tools: : Virtuoso Layout XL,L Editor, Calliber Verification(DRC,LVS)

Role: To develop layout from schematic, floor plan, power

management, clean DRC and LVS.

HANDLED BLOCKS:

MIXER

POWER AMPLIFIER

SWITCH

PROFESSIONAL TRAINING:

Undergone intensive training in CUSTOM LAYOUT from Institute of Silicon

Systems Pvt Ltd., Hyderabad for 3 months.

DIGITAL LAYOUT PROJECTS:

Project 1: STANDARD CELLS LAYOUT DESIGNING

Tools : Virtuoso Layout XL,L Editor, Assura

Verification(DRC,LVS)

Cells designed : INVERTER NAND

AND NOR

OR OAI

MUX D-flip flop

Targeted technology : TSMC 130nm

Role : Drawing the stick diagram from spice net list and to

develop the layout and verifying DRC and LVS.

Challenges : Maintain cell height as constant as 3.69,

Maintain prboundary width in multiples of contact

pitch(0.34),

Delivering the

project on time.

ANALOG LAYOUT PROJECTS:

OPAMP

DAC

BANDGAP

LEVEL SHIFTER

PLL

Skills reached:

. Knowledge on device matching, latch up effects,

. Understanding signal flow to acquire an optimum floor plan and

power plan,

. Solving the problems on Deep sub micron techniques,

. Providing the deep nwell process,

. Providing shielding for critical signals,

. Following anteena rules,

. Knowledge on deep sub micron effect,

. Solving the DRC/LVS issues,

. Experience on L,XL Editor.

. To level routing,

. Gds2 conversion

Under graduate Project Details:

Project Title : skin tone based secret data hiding (steganography).

Tool Used:MATLAB

Role : Team Leader

Description: Maintaining the secrecy of digital information

when being communicated over the Internet.

EDUCATIONAL QUALIFICATION:

B.tech. Electronics & communication Engineering(2009-2013)

Chebrolu Engineering college, JNTU KAKINADA

I hereby declare that the information furnished above is true to the best

of my knowledge.

Date:

Place:

(J V Vijaya Kumar)

Contact this candidate