Project Training
Resume:
Sheetal K S
E-mail: ******.**@*****.***
Ph. no: +919*********
CAREER OBJECTIVE:
I would like to be a part of organization where I could use and enhance my knowledge and talent for the development of both organization and myself. ACADEMIC PROFILE:
Course Year Institution University Result (avg.)
M.Tech
2013 - 2015
PESIT, VTU,
Bangalore Belgaum 65%
(VLSI Design &
Embedded System)
BE
2013
SRSIT, Bengaluru VTU, 70%
(ECE) Belgaum
PUC
2009
Vijaya PU college PU Board, 73.3%
Bangalore
(PCMB)
X standard
2007
St. Mira’s high SSLC Board 83%
school, B’lore Bangalore
TECHNICAL SKILLS:
Languages : Verilog HDL, Basics of C and C++.
Tools : Cadence Virtuoso schematic editor & Digital encounter, Matlab Questasim, Modelsim, Xilinx.
ACHIEVEMENTS AND TRAININGS:
Participated in school annual Rally and Ravel at Shanthi Gruha SHQ conducted by The Bharat scouts and guides Karnataka.
Participated in NCC combined annual training camp -2007 and secured second place in self defense.
Participated in Internship Training at HAL.
Participated in Vocational Training conducted by BSNL.
Participated in workshop sponsored by TEQIP 2 on Artificial neural networks
& real time operating system.
AREA OF INTEREST:
Analog and Digital Logic Design.
CMOS Technology
VLSI Verification
PROJECTS UNDERTAKEN:
PROJECT 1:
Title : IMPLEMENTATION OF LOW FREQUENCY TRANS-RECEIVER USING QPSK MODULATION SCHEME
Tool Used : Matlab, Xilinx
Description :
The project involves development of QPSK modulation and demodulation scheme for Software defined radio, development phases are: 1. Developing the modules in Matlab simulink and Matlab system generator and the results are compared.
2. Developing verilog code for the tested modules and the results are tested. 3. Developed verilog code and the Matlab generated code are compared in Power, Delay and Area through Cadence tool.
4. The developed modules are integrated with existing BCH encoding and decoding blocks and results are tested.
5. Developed verilog code is implemented on FPGA and is tested for performance.
PROJECT 2:
Title : DESIGNING OF FIR FILTER
Tool Used : Xilinx
Description :
a. FIR filters feature the advantage of linear phase, stability, fewer finite precision errors, and efficient implementation.
b. The proposed method presents a programmable digital Finite Impulse Response (FIR) filter for high-performance applications. PROJECT 3:
Title :CONTROL AREA NETWORK (CAN).
Tool Used :Xilinx
Description :
1. Control area network (CAN) is a two- wired, half duplex, high-speed network system,
2. It is far superior to conventional serial communication protocol such as RS232
3. With regards to functionality and reliability and yet CAN implementations are more cost effective.
PROJECT 4:
Title : VLSI IMPLEMENTATION OF MAC UNIT
Tool Used : Xilinx
Description :
1. The objective of this project is to deisgn a MAC unit using modified Booth algorithm.
PROJECT 5:
Title : HIGH PROTECTION VOICE IDENTIFICATION BASED BANK LOCKER SECURITY. Tool used :Keil,voice recognisation kit.
Description :
I. The speech recognisation system is a completely assembled and eases to use programmable speech recognisation circuit,
II. It has 8-bit data out which can be interfaced with any microcontroller for further development.
PROJECT 7:
Title : FLEX SENSOR OPERATED ROBOTIC ARM
Team members : 4
Description :
1. Robotic arm which is virtually created and controlled using a flex sensor 2. Here when we move a single finger or any hand movements has to be replicated on the robotic arm.
3. So in many applications like auto mobile industry, chemical industry where humans can’t handle that time we can use these robotic arms. PERSONAL PROFILE:
Name : Sheetal K S
Date of Birth : 18.12.1991
Father’s Name : Mr. Shyam Sunder K
Sex : Female
Marital Status : Single
Nationality : Indian
Religion : Hindu
Languages Known : Kannada, English, Telugu and Hindi. Hobbies : Reading novels, listening music.
DECLARATION:
I hereby declare that above mentioned information are true and correct to best of my knowledge.
Sheetal K S
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