Engineer Design

Avik Majumdar #*** Papaiah Garden, Marathahalli,

Male, Indian Bangalore - 560037

Phone: +91-725*******

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Objective

Seeking entry level assignments in the domain of VLSI/ ASIC/ FPGA/ DESIGN

Verification with an organization of repute, supported by innovative and

challenging work environment that can provide me with a diversified

exposure to different technologies and various cultures.

Synopsis

. M.Tech in VLSI Design with nearly 4 years of total experience including

nearly 3 years in Design & Verification Industry.

. Presently working with SION Semiconductor as a Front end Design and

Verification from Jan 2014-till date.

. Worked with Alcatel-Lucent (Payroll: Adecco) as a Front-End Verification

engineer from 2009-2011.

. Worked with Shriram Transport Finance Pvt. Ltd as a Management Trainee

from 2008-2009.

Education

2014 SRM University, Chennai

SRM University 8.23(CGPA) M.TECH

2008 Mallabhum Institute of Technology, WB

WBUT 7.79(CGPA) B.TECH

2004 Kendriya Vidyalaya, Barrackpore, WB

CBSE 61% Class XII

2001 Kendriya Vidyalaya, Dinjan, Assam

CBSE 55%

Class X

Technical Skills

Languages System Verilog, UVM, Verilog, Hspice, C, C++, Perl.

Layout Tools Microwind, CADENCE (Virtuoso, Assura,

Spectra).

VLSI Tools Xillinx, Altera Quartus II.

Others FPGA: Spartan-3E, Virtex-4,

CycloneII & IV; Protocols: UART, DDR3,

PCIe, USB, Ethernet.

Certification and Publication

. Published Paper: Avik Majumdar, J.K.Kasthuri Bha " A Fast-Locking All-

Digital Delay Locked Loop using a Register Controlled Technique" Volume

05, Page no. 785-793, Article-03242; IJVES-Y14-03242, March 2014, ISSN:

2249-6556.

. Vocational training on communication system (PLCC, SCADA and Satellite

Communication) from WBSEB on 2007.

. Certificate of Appreciation by SRM University for conducting one month

Software Training Program on Cadence Virtuoso to junior PG students of

SRM University on March-April 2014

Industrial Projects

Project Undertaken in SION Semiconductor :

Title : Advanced High Performance Bus (AHB) Protocol

Platform : UVM, System Verilog, QuestaSim

Description : It was designed to Connects multiple masters to multiple

slave using AHB interconnect and verified using UVM methodology and

libraries.

Role : As a Design and Verification Engineer.

Project Undertaken in SION Semiconductor :

Title : Implementing and design a I2C controller design for

serial EPROM.

Platform : Xilinx ISE, ModelSim, Spartan 3E FPGA kit

Description : The design used with a microprocessor to read the

configuration data from a serial EEPROM that supports an I2C protocol. I2C

master using 7-bit addresses and providing random reads cycles only.

Implemented the design on FPGA

Role : As a Design Engineer.

Project Undertaken in Alcatel-Lucent :

Title : Advanced eXtensible Interface (AXI) Protocol

Platform : System Verilog, QuestaSim

Description : It aimed at developing roles for a project based on the

requirements. All the parts of testbench (Transaction, Generator/

Sequencer, BFM/Driver, Interface, Monitor, Checker/ Scoreboard, Agent and

Environment) is developed in SystemVerilog. Directed testcases and

Constrained-random testcases are written to perform operations.

Role : As a Verification Engineer.

Project Undertaken in Alcatel-Lucent :

Title : Memory Controller

Platform : System Verilog, QuestaSim

Description : A universal Memory Controller core which supports a variety

of memory devices, flexible timing and predefined system startup from a

Flash or ROM memory. Functional verification testbench is developed in

system verilog.

Role : As a Verification Engineer.

Academic Projects

Educational Projects

Project Undertaken in SRM University during M.Tech : Final year Project

Title : A Fast-Locking All-Digital Delay Locked Loop using a

Register Controlled Technique

Platform : CADENCE (Virtuoso, Assura, Spectra), Hspice, Tanner.

Description : ADDLL using a register controlled technique for wide-range

operation and low-jitter performance is proposed and implemented. A circuit

is designed in 0.18-?m technology.

Project Undertaken in SRM University during M.Tech :

Title : Design and Verification Dual Port RAM using system

verilog

Platform : System Verilog, QuestaSim

Description : Prepared a class based layered test bench environment in

SystemVerilog (SV) to verify Memory for Read, Write and Reset operations in

Dual Port RAM using single Interface.

Project Undertaken in Mallabhum Institute of Technilogy during B.Tech :

Final Project

Title : Multipartitioning using Genetic Algorithm

Platform : C/C++, Pspice.

Description : Objective is to partition the circuit into parts such that

the sizes of the components are within prescribed ranges and the number of

connections between the components is minimized.

Area of Interest

. ASIC Design, RTL Design, Digital Logic Design.

. Functional Verification.

. SoC Verification.

. Physical Design and Verification.

. FPGA Implementation.

Extra - Curricular Activities

. Successfully won Cricket Championship at college level.

. Participated in several Cultural and Sports activities at school and

college level.

Other Information

Date of Birth : 19th March 1986

Languages Known : English, Hindi and Bengali

Permanent Address : C/O D.K.Das, 12/C Milan Park,

Kalianibas, Kolkata, PIN-700122, West Bengal

Language Known : English, Hindi and Bengali

DECLARATION

I hereby declare that the above mentioned information is correct up

to my knowledge and I bear the responsibility for the correctness of the

above mentioned particulars.

Contact this candidate