Design High School

VIVEK SHARMA

VPO Dangri Tehsil Nadaun District Hamirpur (H.P.), India 177048

Phone: +917*********; E-mail:*********@*****.***

CAREER OBJECTIVE

I want to provide creative solutions as a team member in terms of architecture definition, circuit design, verification

plan, support for test development and problem solver with high accountability.

ACADEMIC QUALIFICATIONS

• Advance Diploma in ASIC Design, RV-VLSI Institute, Bangalore, 2014

• Bachelor of Engineering in Electronics & Communication, Maharishi Markandeshwar Engineering College,

Maharishi Markandeshwar University(H.R) CGPA : 8.61/10, 2013

• 12th, Him Academy Public School Hamirpur, 72 %, 2009

• 10th, Govt. High School Dangri, Hamirpur, 72%, 2007

ACADEMIC PROJECTS

Title: Verification of SoC sub-system

Duration: March-April 2014

Team Size: Individual

Organization: RV-VLSI

Summary: The AHB-Wishbone sub-system comprised of wishbone complaint serial communication peripherals like

SPI, I2C and UART. Verified by writing test sequences using UVM methodology.

Tools Used: Questa Simulator

Title: Verification of FIFO

Duration: January 2014

Team Size: Individual

Organization: RV-VLSI

Summary: FIFO (First in First Out) is used to buffer data and used in Inter-Process communication. Realized the

design using Verilog HDL and verified it by writing a self-checking test bench in System Verilog.

Tools Used: Questa Simulator

Title: Verification of UART module

Duration: December 2013

Team Size: Individual

Organization: RV-VLSI

Summary: The design under verification is a fully functional, synthesizable universal asynchronous receiver

transmitter soft core with microprocessor bus, ideal for embedded processor applications or system-on-programmable-

chip.

Tools Used: Questa Simulator

Title: ALU and RAM Verification

Duration: December 2013

Team Size: Individual

Organization: RV-VLSI

Summary: RAM is a digital storage device. The advantage of RAM is we can get input/access at any time.

In verilog I have verified RAM. Arithmetic logic unit is a digital circuit that performs integer arithmetic and logical

operations.

Tools Used: Questa Simulator

Title: Microcontroller Based Cutting Tool

Duration: March-April 2012

Team Size: 3

Summary: To enhance the features of microcontroller in cutting materials. It was demo or minor project to controller

the estimation of size of different materials.

TECHNICAL SEMINAR

Durdarshan Delhi, India learnt usage of networking in the programs recording, live telecast. All

processing that how it works. Data transfer exchange all the different modules in the station.

PROFESSIONAL AFFILIATION

• Good Knowledge of Verilog RTL coding, System Verilog, UVM methodology.

• Good Knowledge of Digital Design Concepts.

• Good exposure to technology by undergoing additional training in VLSI.

• Knowledge of IC Fabrication process.

COMPUTER SKILLS

• Languages: Verilog HDL, System Verilog

• Methodology: UVM

• EDA Tools: Cadence, Modelsim, Synopsys

• Operating Systems: WINDOWS, LINUX

• Scripting Languages: PERL

• Other Software : M S Office

AWARDS & ACHIEVEMENTS

• First prize, MicroHouse event at HAPS in choreography.

• First prize in Cricket Tournament at INTRA Level College Competition.

• First prize in TLM Competition at Block Level.

• Active member of ECES Society, organized many events in society.

• Workshop on Emerging Technologies by Labs N Racks.

• Participated in Combined Annual Training Camp of National Cadet Corps.

PERSONAL DETAILS

Father’s Name Krishan Dev Sharma

Nationality Indian

Date of Birth 20 Aug, 1993

Gender Male

Marital Status Single

Languages known English (Fluent), Hindi (Native)

Valid Passport Yes (L1976762)

Permanent Address VPO DANGRI TEHSIL NADAUN DISTRICT Hamirpur (Himachal Pradesh)

DECLARATION

I declare, to the best of my knowledge that the information given above is true.

DATE:

PLACE: BANGALORE VIVEK SHARMA

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