| Resume alert | Resumes 21 - 30 of 448 |
Sales, Detail Oriented Quality Standards, Cybersecurity and Computer
San Jose, CA
... TECHNICAL SKILLS Sales, Detail Oriented Quality Standards, Linux, MacOS, iOS, Windows, Microsoft Word, PowerPoint, Microsoft Excel, Computer Hardware and Software Troubleshooting, Network Configuration, Verilog, VHDL, FPGAs, MOSFETs, CMOS, PMOS, ... - 2023 Apr 02
... TECHNICAL SKILLS Sales, Detail Oriented Quality Standards, Linux, MacOS, iOS, Windows, Microsoft Word, PowerPoint, Microsoft Excel, Computer Hardware and Software Troubleshooting, Network Configuration, Verilog, VHDL, FPGAs, MOSFETs, CMOS, PMOS, ... - 2023 Apr 02
RF/Analog design engineer
Downtown San Jose, CA, 95113
... (diode, CMOS, Bipolar, FINFET), analog and RF circuits (current mirror, op-amp, bandgap, LDO, ADC, LNA, PLL, mixer, etc.) Proficiency in Cadence, Synopsys, MATLAB, Unix and Linux operation systems, Microsoft office, some Verilog and some C language. ... - 2023 Feb 08
... (diode, CMOS, Bipolar, FINFET), analog and RF circuits (current mirror, op-amp, bandgap, LDO, ADC, LNA, PLL, mixer, etc.) Proficiency in Cadence, Synopsys, MATLAB, Unix and Linux operation systems, Microsoft office, some Verilog and some C language. ... - 2023 Feb 08
Electrical Engineer
Fremont, CA
... Verilog / VHDL experience Experience with OrCAD schematic capture and Allegro PCB layout – Extremely good at OrCAD, some experience with Allegro – need to see what the latest tool facilities are – principles of design remain the same more or less. ... - 2023 Jan 02
... Verilog / VHDL experience Experience with OrCAD schematic capture and Allegro PCB layout – Extremely good at OrCAD, some experience with Allegro – need to see what the latest tool facilities are – principles of design remain the same more or less. ... - 2023 Jan 02
Customer Support Processor
Scotts Valley, CA
... Wrote the GC1115 specification, all Matlab code for bit-accurate device simulation, generated ~600 test vectors for RTL (Verilog) testing, briefed customers on the GC1115, wrote the data sheet. Managed the GC1115 release to market (RTM). Jan 00 – ... - 2022 Nov 23
... Wrote the GC1115 specification, all Matlab code for bit-accurate device simulation, generated ~600 test vectors for RTL (Verilog) testing, briefed customers on the GC1115, wrote the data sheet. Managed the GC1115 release to market (RTM). Jan 00 – ... - 2022 Nov 23
Customer Service It Technician
Downtown San Jose, CA, 95113
... Test board bring ups Gaming PC builds HW & SW upgrades on desktop and laptop PCs SOFTWARE: MobaXterm Vivado C++, Python, Verilog Microsoft Office Autocad Linux/Windows Interests: PCB Integration Microelectronics Computer Architecture Schematic ... - 2022 Oct 20
... Test board bring ups Gaming PC builds HW & SW upgrades on desktop and laptop PCs SOFTWARE: MobaXterm Vivado C++, Python, Verilog Microsoft Office Autocad Linux/Windows Interests: PCB Integration Microelectronics Computer Architecture Schematic ... - 2022 Oct 20
Design Engineer Product
San Jose, CA
... with IC Design and test/evaluation skill can be utilized SUMMARY Hands-on experience in designing the High Speed PMIC, PLL, RT-OSC, DAC and many Analog & Mixed Signal Design using Cadence Toolset, Analog Artist, Spectre, HSPICE, and Verilog-XL. ... - 2022 Apr 29
... with IC Design and test/evaluation skill can be utilized SUMMARY Hands-on experience in designing the High Speed PMIC, PLL, RT-OSC, DAC and many Analog & Mixed Signal Design using Cadence Toolset, Analog Artist, Spectre, HSPICE, and Verilog-XL. ... - 2022 Apr 29
Electrical engineering intern
Santa Clara, CA, 95050
... [https://tinyurl.com/ybvnzghc] SKILLS Programming Languages · Python C++ C Verilog HTML CSS JavaScript LEGv8 (ARM assembly simulator) R Software · EagleCAD SolidWorks MATLAB Docker Vivado Arduino IDE PSpice Simulation SQL Hardware · 3D Modeling and ... - 2021 Jun 18
... [https://tinyurl.com/ybvnzghc] SKILLS Programming Languages · Python C++ C Verilog HTML CSS JavaScript LEGv8 (ARM assembly simulator) R Software · EagleCAD SolidWorks MATLAB Docker Vivado Arduino IDE PSpice Simulation SQL Hardware · 3D Modeling and ... - 2021 Jun 18
Digital and Physical Design Engineer, Verification Engineer
Santa Clara, CA
... of Engineering, Electronics and Telecommunication Engineering GPA: 9.12/10 TECHNICAL SKILLS Programming Languages: Verilog, SystemVerilog, Python Tools: Cadence Virtuoso, QuestaSim, Quartus, HSPICE, Xilinx Vivado, PrimeTime(STA), Innovus(PnR) ... - 2021 May 30
... of Engineering, Electronics and Telecommunication Engineering GPA: 9.12/10 TECHNICAL SKILLS Programming Languages: Verilog, SystemVerilog, Python Tools: Cadence Virtuoso, QuestaSim, Quartus, HSPICE, Xilinx Vivado, PrimeTime(STA), Innovus(PnR) ... - 2021 May 30
Engineering Manager Design Engineer
Los Gatos, CA, 95032
... o Environment -- Linux o Language -- Python & PyQT4 Took over existing Memory Compiler software created by TI software team and collaborated with memory designers to enhance the tool to support additional EDA views (Mixed Signal Verilog, Cadence EPS ... - 2021 May 24
... o Environment -- Linux o Language -- Python & PyQT4 Took over existing Memory Compiler software created by TI software team and collaborated with memory designers to enhance the tool to support additional EDA views (Mixed Signal Verilog, Cadence EPS ... - 2021 May 24
Java Engineer
Mountain View, CA
... GPA: 3.66/4.0 - Made Dean’s List in Fall 2018 to Fall 2019, and Spring 2020 Relevant Courses: - Data Structures and Algorithms using Java, Linear Algebra, Formal Language and Computations Technical Skills: - Java, C++, Verilog, some Javascript, some ... - 2021 May 06
... GPA: 3.66/4.0 - Made Dean’s List in Fall 2018 to Fall 2019, and Spring 2020 Relevant Courses: - Data Structures and Algorithms using Java, Linear Algebra, Formal Language and Computations Technical Skills: - Java, C++, Verilog, some Javascript, some ... - 2021 May 06