Dock J. Lee

adqw3f@r.postjobfree.com cell : 408-***-****

OBJECTIVE Seeking a Product Engineer position where my knowledge and experience associated with IC Design and test/evaluation skill can be utilized

SUMMARY Hands-on experience in designing the High Speed PMIC, PLL, RT-OSC, DAC and many Analog & Mixed Signal Design using Cadence Toolset, Analog Artist, Spectre, HSPICE, and Verilog-XL.

Hands-on experience in Full-chip Layout Floor-planning, and Layout-verification using Cadence Virtuoso-XL/Opus, Assura & Dracula DRC/ LVS, Calibre DRC/LVS.

Hands-on experience in Cell Layout design & verification considering ESD /Latch-up rule.

Knowledge of CMOS/Bipolar Process & Design, layout matching issue, Latch-up theory and prevention techniques, ESD and protecting techniques, noise issue, and high frequency issues.

Knowledge of Verilog HDL, Matlab and UNIX Operating system.

Experienced in operating the test program written in Visual Basic or C++.

Strong desires to learn and explore new technologies.

EXPERIENCE Computer Server Rack Tester, Synnex Corporation Fremont 3/14 – present

Execution of Iperftest, Power-cycle, Stress-test, Burn-in test and trouble-shooting for the Amazon and the Facebook Computer Servers

Design Engineer & Lead, Integrated Memory Logic San Jose 3/09 – 7/13

Working on Multi-functional Power Management IC (Buck, Boost, LDO, High-voltage Level- Shifter, Bias Circuit, I C) for Notebook LCD Panel

Design & Implementation of Buck, Boost, Local-oscillator, current-sensing scheme, over-current/voltage protection, Soft-start scheme, Error-amplifier with built-in-capacitor-multiplier, PWM-comparator, LDO, High-power-output-driver, schmitt-trigger-in-buffer, High-voltage level-shifter (1Vpp 60Vpp : -20V/+40V), Bandgap-reference and bias-circuit in One chip.

VCOM Voltage Calibrator with DAC including Bandgap Trimming scheme.

Lead the project including Floor-plan for full-chip and Tape-out!

Hands-on output driver & pre-driver cell layout and placement into the chip.

Developed the robust High-voltage level-shifter architecture.

PDK and DRC/LVS Rule-deck installation and verification for new High-Voltage process.

use 0.5um, 0.35um, 0.25um, 0.18um CMOS process.

Staff Design Engineer, Integrated Device Technology San Jose 8/97 – 1/09

Working on many Clock Synthesizers using PLL(Phase Locked Loop) and Zero Delay Buffer using DLL(Delay Locked Loop) for Printer or Set-top box

Design and layout up to 1.5GHz VCO using on-chip inductor.

Design and implement Dual-Modulus dividing Pre-scaler

Design and Simulation of LVDS/LVPECL Output-Buffers.

Design and hands-on floorplan of up to Three-PLL-in-one-chip Platform.

Design and implement of PFD (Phase Frequency Detector), Charge-pump, VCO, Divider, Input/Output-Bidirectional-buffer, Bandgap-reference.

Developed E PROM Built-in Clock Synthesizer.

Hands-on Layout Bidirectional-buffer block.

Senior Design Engineer, Pericom Semiconductor, Inc. San Jose 10/96 – 8/97

Design and tape out of Zero Delay Buffer

Senior Design Engineer Raytheon Semiconductor, Inc. Mountain View 4/93 – 10/96

Mainly Worked on DC-DC Converters using BiCMOS process

Design and development of DC-DC converter using BiCMOS process.

Design verification of Switched capacitor Filter.

Analog Cell IP design including ADC, DAC, Filters, OP-amp, and Bandgap reference

Full chip ASIC Design and layout support to develop the Bar-code sensor.

Design Engineer & Manager, Samsung Electronics, Inc. Kihung, Korea 11/83 – 4/93

Worked for the development of Cell Libraries/Gate Array/Design Automation as well as many Bipolar ICs for communication devices like AM/FM/NTSC/PAL systems

1H CCD Delay Line using CCD + CMOS process

Developed the cell libraries, Gate-array master-slices, and design automation algorithm.

Design and development of FM-Front-End, IF Amps, Mixers, FM Stereo Decoder, RF Amps, Audio Power Amps, Graphic Synthesizers, Motor Speed Controllers, Bandpass Filters

and etc.

EDUCATION M.S. in Electrical Engineering, Santa Clara University, Santa Clara, California

B.S. in Electrical Engineering, KyungHee University, Seoul, Korea

REFERENCES Available upon request US Citizen

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