EDUCATION

Diego Munoz

**** **** ******, *** *********, CA adu70j@r.postjobfree.com 650-***-**** MS degree in Electrical Engineering, December 2020. San Jose State University, San Jose, CA, USA

Pertinent Coursework:EE221 Semiconductor devices, EE222 Advance integrated devices, EE210 linear systems theory, EE220 RFIC Design I, EE230 RFIC design II, EE288 data conversion/analog mixed signal ICs,

BS degree in Electrical Engineering, August 2018. San Francisco State University, San Francisco, CA, USA EXPERIENCE

Math Fellow, Saga Education and AmeriCorps, August 2021 to present.

Create course content for math subjects for students.

Create google slides presentation for professional development for the team.

Contact parents regarding student’s progress and concerns.

Create google meets for specifics events given by our Site Director. Teaching Assistant and Instructional Student Assistant, San Jose State University, January 2020

TA for EE122, Electronic design I

Improved presentation and teaching skills, improved and reinforced my technical and academic knowledge PROJECTS

Analog to Digital Converter: San Jose State University, San Jose, CA. Spring 2020-Spring2020

Designed 10-bit pipeline ADC using 1.5-bit stage, with sample rating of 50Ms/s and FoM of 1pJ/step conversion

Designed 10-bit SAR ADC with sample rating of 5Ms/s and FoM of 1pJ/step conversion, 8.5 bits of ENOB

Conducted designs of the comparator, high gain opamp, capacitor array.

Bootstrap Switch with different architecture were design to achieve greater than 10-bit accuracy and SNR>60dB Sampling frequency used was 100MHz and supply voltage 1V Bandgap Voltage Reference and high gain op-amp: San Jose State University, San Jose, CA. Fall 2019

Designed bandgap with 1.2V of temperature-independent voltage reference and 25uA of PTAT current

Designed the high gain and high swing operational amplifier with 90dB of gain, 30MHz of unity bandwidth, and 60 of phase margin using folded cascode structures 1.9GHz Phase look loop (PLL): San Jose State University, San Jose, CA. Fall 2019

Designed type II charge-pump PLL at 1.92GHz including Phase Frequency Detector (PFD), Charge pump, loop filter, Voltage Control Oscillator (VCO), Frequency Divider

Implemented ring VCO and LC-VCO structures for the PLL Low Noise Amplifier (LNA): San Jose State University, San Jose, CA. Fall 2019

Designed LNA with less than 3dB of noise figure, 25dB of Gain, and -17dBm of IIP3

Implemented common gate LNA and common source with inductive degeneration structures TECHNICAL SKILLS

Understanding of semiconductor devices (diode, CMOS, Bipolar, FINFET), analog and RF circuits (current mirror, op-amp, bandgap, LDO, ADC, LNA, PLL, mixer, etc.)

Proficiency in Cadence, Synopsys, MATLAB, Unix and Linux operation systems, Microsoft office, some Verilog and some C language.

Bilingual Spanish and English

PROFESSIONAL REFERENCES

Prof. Sotoudeh Hamedi-Hagh, San Jose State University, adu70j@r.postjobfree.com, 408-***-****

Prof. Sang Soo Lee, San Jose State University, adu70j@r.postjobfree.com, 408-***-****

Prof. Hamid Mahmoodi, San Francisco State University, adu70j@r.postjobfree.com 415-***-****

Jack Marin, Learning Coordinator at Saga Education, adu70j@r.postjobfree.com 207-***-****

Starling Archibald, Site Director at Saga Education, adu70j@r.postjobfree.com 205-***-****

Kenzie Confer, Math fellow at Saga Education, adu70j@r.postjobfree.com 843-***-****

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