| Resume alert | Resumes 31 - 40 of 48 |
ASIC,Verilog, System verilog, UVM
North Plains, OR
... circuit design and verification, Power analysis • Good academic knowledge on ASIC Modeling and Synthesis, Logic/Verification Design, ASIC Physical Design • Experience in C,C++,PERL,TCL,Verilog,System Verilog • Exposure to Pre-Silicon Verification. ... - 2014 May 27
... circuit design and verification, Power analysis • Good academic knowledge on ASIC Modeling and Synthesis, Logic/Verification Design, ASIC Physical Design • Experience in C,C++,PERL,TCL,Verilog,System Verilog • Exposure to Pre-Silicon Verification. ... - 2014 May 27
Software Engineer Project
Portland, OR
... Linux/UNIX, Mac OS X, Windows environments Git / Gerrit / Mercurial / Subversion / TFS Meeting management gEDA / OrCAD / Verilog / VHDL Model/View/Controller architecture Arduino / AVR / PIC Microcontrollers Multi-platform code design FreeRTOS / ... - 2012 Nov 20
... Linux/UNIX, Mac OS X, Windows environments Git / Gerrit / Mercurial / Subversion / TFS Meeting management gEDA / OrCAD / Verilog / VHDL Model/View/Controller architecture Arduino / AVR / PIC Microcontrollers Multi-platform code design FreeRTOS / ... - 2012 Nov 20
Sales Engineer
Portland, OR
... I was their first employee Design and Development of USB 2.0 functional IP Core using Verilog Design and modeling of RDRAM memory controller Implementation of the decoder logic of the PCS sub layer of the 10GB Ethernet Educational Qualifications ... - 2012 Nov 11
... I was their first employee Design and Development of USB 2.0 functional IP Core using Verilog Design and modeling of RDRAM memory controller Implementation of the decoder logic of the PCS sub layer of the 10GB Ethernet Educational Qualifications ... - 2012 Nov 11
Sales Supply Chain
Portland, OR, 97086
... Utilized various local employment Java) Telecom, HW/E (Verilog, HDL), Agencies to identify hard to find candidates. EE’s (Embedded and firmware), Network Engineers, Security Specialists, Project Engineers, EXPERIENCE Contract Specialists Associate ... - 2012 Aug 30
... Utilized various local employment Java) Telecom, HW/E (Verilog, HDL), Agencies to identify hard to find candidates. EE’s (Embedded and firmware), Network Engineers, Security Specialists, Project Engineers, EXPERIENCE Contract Specialists Associate ... - 2012 Aug 30
Software QA Analyst/Engineer
Portland, OR, 97006
... Operating Systems: UNIX, Windows XP & Vista, Linux, Bourne, C shell, DOS and Windows tools EDA Tools: Verilog & VHDL Simulators, Layout and Timing Analysis, Schematic development, some place and route tools. Database Work: MySQL and Sybase. Fluent ... - 2011 May 09
... Operating Systems: UNIX, Windows XP & Vista, Linux, Bourne, C shell, DOS and Windows tools EDA Tools: Verilog & VHDL Simulators, Layout and Timing Analysis, Schematic development, some place and route tools. Database Work: MySQL and Sybase. Fluent ... - 2011 May 09
Human Resources Insurance Agent
Vancouver, WA, 98684
... Candidates on Demand -recruited for process engineers, project managers, IT and banking INTEL Corporation - recruited for SW, hardware and process engineers with experience in integrated circuits, CAD, unix, board design, verilog coding, validation, ... - 2011 Mar 14
... Candidates on Demand -recruited for process engineers, project managers, IT and banking INTEL Corporation - recruited for SW, hardware and process engineers with experience in integrated circuits, CAD, unix, board design, verilog coding, validation, ... - 2011 Mar 14
Project Design
Portland, OR, 97201
... May 2006 COMPUTER SKILLS Programming Languages : C, C++, Python, Verilog, VHDL, Assembly language, Visual C++. Design tools : ModelSim, Veloce, Xilinx (ISE, XPS, EDK), Microsoft Visual Studio, Dev C, GCC, ASM51. Operating Systems : WINDOWS XP, ... - 2010 Oct 30
... May 2006 COMPUTER SKILLS Programming Languages : C, C++, Python, Verilog, VHDL, Assembly language, Visual C++. Design tools : ModelSim, Veloce, Xilinx (ISE, XPS, EDK), Microsoft Visual Studio, Dev C, GCC, ASM51. Operating Systems : WINDOWS XP, ... - 2010 Oct 30
Design Electrical
Hillsboro, OR, 97124
... TECHNICAL SKILLS: Languages: System Verilog, Verilog, VHDL, C, C++, Perl, Matlab, Labview, Arduino. Simulation, Layout and Synthesis Tools: Xilinx ISE, Pspice, Simulink, OrCAD, ModelSim, Synopsys, L-EDIT. Operating Systems: Unix, Windows XP, Windows ... - 2010 Oct 05
... TECHNICAL SKILLS: Languages: System Verilog, Verilog, VHDL, C, C++, Perl, Matlab, Labview, Arduino. Simulation, Layout and Synthesis Tools: Xilinx ISE, Pspice, Simulink, OrCAD, ModelSim, Synopsys, L-EDIT. Operating Systems: Unix, Windows XP, Windows ... - 2010 Oct 05
Engineer Design
Portland, OR, 97214
... Windows NT Server & Workstation 3.51, Novell NetWare 4.10 & 4.10 SMP, UnixWare 2.02 Installation and Administration HSPICE & PSPICE, MAGIC CAESAR, System Verilog, VeriLog HDL, VHDL, ABEL, PALASM4, ORCAD, SCHEMA and VIEW Logic CAD Tools. Familiar ... - 2010 Sep 15
... Windows NT Server & Workstation 3.51, Novell NetWare 4.10 & 4.10 SMP, UnixWare 2.02 Installation and Administration HSPICE & PSPICE, MAGIC CAESAR, System Verilog, VeriLog HDL, VHDL, ABEL, PALASM4, ORCAD, SCHEMA and VIEW Logic CAD Tools. Familiar ... - 2010 Sep 15
Design Engineer
Wilsonville, OR, 97070
... Strong knowledge of HDL languages (Verilog, VHDL) and system-level design and analysis tools (Matlab, Simulink) . Strong knowledge of ASIC simulation, synthesis, static timing analysis (STA) and design-for-test (DFT) tools (Design Compiler, ... - 2010 Sep 13
... Strong knowledge of HDL languages (Verilog, VHDL) and system-level design and analysis tools (Matlab, Simulink) . Strong knowledge of ASIC simulation, synthesis, static timing analysis (STA) and design-for-test (DFT) tools (Design Compiler, ... - 2010 Sep 13