Design Engineer

Maxim Smirnov

**** ** ********* ******

Wilsonville, OR, U.S.A.

Tel (home): 503-***-****

Tel (cell): 503-***-****

abk71t@r.postjobfree.com;

abk71t@r.postjobfree.com

Objective

An industrious and experienced team leader and hands-on engineer with an

outstanding record of achievements seeking joining a high caliber ASIC

design engineering team as a design team lead or individual contributor.

Summary

. More then 17 years of hands-on digital and mixed-mode ASIC design

experience, successful technical leadership and innovation

. A holder of US and international patents and author of various technical

publications

. Track record of successful designs from idea to working silicon

. Unique set of skills - from telecom and digital signal processing to

speech and video processing in multimedia SoCs

. Was actively involved in architecture definition, implementation and tape-

out of many SoC ASICs

. Strong knowledge of ASIC and FPGA design methodologies and processes

. Strong knowledge of HDL languages (Verilog, VHDL) and system-level design

and analysis tools (Matlab, Simulink)

. Strong knowledge of ASIC simulation, synthesis, static timing analysis

(STA) and design-for-test (DFT) tools (Design Compiler, PrimeTime, RTL

Compiler, etc.)

. Working knowledge of programming and scripting languages (C/C++, DSP

Assembler)

. Hands-on experience with lab equipments, and ASIC bring up and debugging

process

. Strong knowledge of embedded cores (ARM, Tensilica) and on-chip bus

protocols (AMBA, AHB and AXI)

. Expert in digital image and video processing and compression

. Expert in ESL SoC design flows

Professional Experience

Mentor Graphics Corporation, Wilsonville, OR, USA

Technical Marketing Engineer

09/07-Present time

Reported to the Director of Catapult C Synthesis Product Line. The

responsibilities in this position included defining a long-term roadmap for

the Mentor Graphics' Electronic System Level (ESL) products in general and

Catapult High-Level Synthesis (HLS) in particular. This position required

working closely with customers, engineering and product marketing, refining

the products to meet the market requirements, developing reference designs,

writing marketing requirement documents (MRDs), application notes, white

papers and participating in technical conferences. While holding this

position, led the following projects:

. Catapult High-Level Synthesis 3-5 year roadmap definition

. Feasibility study and a pilot project of Synthesisable Virtual

Platform (SVP), a second generation of ESL design methodology -

proposed the concept of SVP, a link between Virtual Prototyping and

full-chip capable HLS - provided technical leadership and co-

ordination of the multi-site development process; led the development

of "Synthesizable Virtual Platform Language Reference Manual"; acted

as an architect and user source code developer of the reference

design; published and presented a conference paper

. Catapult low-power roadmap - defined the roadmap and developed MRDs

for three HLS power optimization projects

. Distributed pipeline synthesis - proposed the concept of high-level

synthesis of distributed pipelines, developed the MRD and required

Catapult library components and filed a US patent application

. High-level synthesis with multiple clock domains - proposed the

solutions and implemented clock domain crossing Catapult library

components in VHDL and Verilog

ATI Technologies/AMD/Qualcomm, Markham, ON, Canada

Member of Technical Staff

12/01 - 08/07

The responsibilities in this position included RTL implementation system-

level integration of various IP blocks, scientific research, and

architectural design especially of large multimedia SoC blocks. One of the

key members of the ATI handheld engineering team. Played vital role in the

success of IMAGEON Multimedia Processors family, taped out few generations

of IMAGEON family of SoCs, which generated hundreds of millions dollars in

revenue; actively contributed to many design wins with Motorola (Razr, L7,

L6, V3, V4, V5, V6 families) and a few other cell phone makers.

Successfully driven large portion of the SOC chip from feature set

definition to tape-out, provided other teams with technical expertise and

actively participated in chip macro-architecture definition; designed and

verified in Matlab/Simulink several proprietary image processing

algorithms; technically supervised members of the team from junior to mid-

senior level.

The list of projects in this position includes:

. Still/video camera subsystem, which included a video capture module,

video processor, JPEG encoder and real-time memory access controller

- concept, system-level design and RTL implementation; US Patent No.

7,486,297

. Camera digital zoom function - concept, algorithm development, system-

level design and RTL implementation

. ISP for CMOS sensor Bayer RGB signal processing - third-party IP

integration, partial redesign

. MPEG4/H263 video encoder-decoder - third-party IP system-level

integration

. DSP for audio encoder-decoder - third-party IP system-level

integration

. Audio Processor Interface Controller - concept, system-level design

and RTL implementation

. Proprietary graphics texture compression method - concept, algorithm

development and performance verification

. Shared Memory Bandwidth Management System for real-time applications

- concept, performance evaluation, RTL implementation

. Proprietary image noise reduction and sharpening method - concept,

algorithm development and performance verification; US Patent No.

7,599,569

. Alpha Blender - concept, system-level design and RTL implementation

. CMOS Sensor noise calibration for generalized bilateral filter noise

reduction - technically supervised research and development of

calibration procedure, published conference papers

. Wavelet-based noise reduction system - algorithm development

Unique Broadband Systems, Concord, ON, Canada

Senior Systems Architect

06/01 - 09/01

Participated in high-speed wireless Internet access system design, was

responsible for OFDM PHY layer performance verification and base station

hardware system level design.

Xentec, Inc/InSilicon/Synopsys, Mississauga, ON, Canada

Systems Architect

11/99 - 06/01

Joined Xentec, a small Canadian start-up company, at a very early stage as

a fifth employee, actively contributed to company growth and future success

and technically supervised the junior members of the team. The

responsibilities included project management, digital IP design

(architecture design, RTL code development, simulation and synthesis), FPGA

prototyping, assembler code development, and digital and mixed-mode signal

processing algorithm design

Participated in and provided technical leadership for the following

projects:

. BLUETOOTH digital radio architecture and system-level design

. JPEG2000 IP core architecture design

. Architecture and RTL code for a positioning system digital radio

. VHDL/Verilog IP cores of UTOPIA level 3 interface controllers

. VHDL/Verilog IP cores of POS-PHY level 3 interface controllers

. JPEG codec demo board

Various positions in Russian Federation

03/93 to 11/99

As an engineer or project team leader, participated in various projects in

fields of telecommunication, digital speech processing, etc. The list of

design types includes:

. Digital signal processing

. Digital and mixed signal design

. Speech compression devices

. Telephone line modems

. CDMA modems for cellular networks

. BPSK and QPSK modems and FER for satellite communication

. SDH, SONET and ATM

. ASIC design, including layout design

. Software and firmware development

. IP development

. PCB design

. CAD software support

Education

Moscow Power Engineering Institute, MS.E.E., Radio-Electronic Systems,

Diploma with Honours, 1993

Patents & Publications

[1] Milivoje Aleksic, Maxim Smirnov, and Sergio Goma, "Image noise

reduction and sharpening filter", Newsletter of the SPIE Electronic Imaging

Technical Group, Nov 2005, Vol. 16, No. 2, Page 8

[2] Milivoje Aleksic, Maxim Smirnov, and Sergio Goma, "Novel bilateral

filter approach: Image noise reduction with sharpening" Proc. SPIE

International Society for Optical Engineering, vol. 6069, 2006, p. 60690F1.

[3] Radu Gheorghe, Milivoje Aleksic, and Maxim Smirnov, "Novel method of

Euclidean distance calculation for bilateral filtering based on CMOS sensor

noise profiles", Proc. SPIE International Society for Optical Engineering,

vol. 6817, 2008, p. 681708

[4] Smirnov, M.; Takach, A.; "A SystemC superset for high-level synthesis"

Specification & Design Languages, 2009. FDL 2009. Forum on, vol., no.,

pp.1-6, 22-24 Sept. 2009

URL: http://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=5404052&isnumbe

r=5404035

This article is included in "System on Chip Design and Modelling"

course materials in University of Cambridge, Principal lecturer: Dr

David Greaves

[5] Kouramanis, Ioannis; Smirnov, Maxim; Aleksic, Milivoje; "Method and

apparatus for image processing in a handheld device", US Patent No.

7,486,297

[6] Smirnov, Maxim; Aleksic, Milivoje; Goma, Sergiu; "Method and apparatus

for bilateral high pass filter", US Patent No. 7,599,569

[7] "Distributed Pipeline Synthesis for High Level Electronic Design", US

Patent Application filed in 2009

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