Thai Quoc Nguyen

**** *.*. ***** ****** Portland, OR 97214

abk4nj@r.postjobfree.com <mailto:abk4nj@r.postjobfree.com>

Home Phone: 503-***-****

Cell Phone: 503-***-****

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GOALS

To obtain a Hardware Engineer position in an established and/or growing

company where my education, experience and potential can be used to promote

company growth and personal career advancement.

MSEE with over 15 years hardware design experience and strong ASIC/FPGA

design, signal integrity skills for high speed Pentium processor and other

boards. (See Intel Oregon, HP, IMS & Diebold SI work). Experience with High

Speed Digital ASIC/Gate Array/FPGA/FPOA Design using Altera, Xilinx,

Lattice, MathStar and Others. Experience with High Speed Signal Analysis,

3.125 Gbps SERDES & 2.5Gbps PCIe, Eye Diagram Analysis, Design Testing,

Debug and Release to Production. Experience executing Test Plan on the High

Speed Board and Signal Integrity: BER, Electrical/Optical Eye Diagram,

Flight Time, Skew, Jitter & Signal Noise, to prevent problems of EMI, ESD

and Reliability and achieve high speed execution. Experience with Analog

Circuit on Board level Design. Well versed in design, test and lab tools

including: Agilent BERT, Signal Analysis, High Speed Digital Oscillator

Scope and Digital Analyzers. Good working knowledge of Pentium Processor.

Excelent team player and able to contribute immediately.

SKILLS: Design & Testing Tools: HP Network Signal Analysis, Spectrum

Analysis, TDR Impedance Analysis, High Speed Digital Oscillator Scope and

Digital Analyzer. Mentor Graphic/Cadence Schematic Editor. Simulation and

Layout using SUN/HP/PC system. Lattice/Xilinx/Altera and Synario/Synthesis

Tools for ASIC Design using FPGA and HP ASIC Gate Array. Interface the

vendors to build the high volume ASIC Chip in Intel, HP & Diebold.

Chip Hardware Controller and Microprogramming. Very Good Debug/Solve the

Problems on ASIC Chip and High Speed & Analog Board Level Design. High

Level Languages: C- Languages (in Graphics, non-linear and numerical

analysis programming), PASCAL and FORTRAN. Low Order Languages: INTEL

80386/486, 8086/88 & 808/85, MC68000 & 6800 Assembly Languages. IBM PC

XT/AT Hardware 8086, 80286, 80386, 80486, Pentium, Pentium Pro Motherboard

and I/O, PowerPC Architecture System Design, EGA, VGA, IDE & SCSI Hard Disk

Controller Board. Windows NT Server & Workstation 3.51, Novell NetWare 4.10

& 4.10 SMP, UnixWare 2.02 Installation and Administration HSPICE & PSPICE,

MAGIC CAESAR, System Verilog, VeriLog HDL, VHDL, ABEL, PALASM4, ORCAD,

SCHEMA and VIEW Logic CAD Tools. Familiar with Mainframe Computers:

UNIX/VAX, IBM, GOULD & HONEYWELL Systems.

PROFESSIONAL EXPERIENCE

Stilwell Baker Inc. (Hillsboro, Oregon) Aug. 2010 -

Present

SENIOR ELECTRICAL ENGINEER,

Working on Master Controller Board for Deep Photonics Laser System:

schematics & packaging by Altium. Designed Microcontroller with Rabbit

Microprocessor, Dynamic-C and other interface control circuits for System

Laser.

MathStar Inc. (Hillsboro, Oregon) Mar. 2008 - June

2008

FPOA SYTEM DESIGN ENGINEER,

Completed programmable FPOA Vegas Prime board: schematics & packaging by

Cadence Allegro. Working on Verilog codes Xilinx Vertex-5 8-lanes PCIe

version 2 & DDR2 memory controller, LVDS & GPIO buses.

Lightfleet Inc. (Camas, Washington) Sept. 2006 -

Mar. 2008

SENIOR HARDWARE DESIGN ENGINEER,

Completed high speed optical test board: 3.125Gbps Laser Emitter and Photo-

Detector circuits design to test the new Lighfleet invent for the high

speed light interconnection in the next high tech generation. Designed

optical power control circuit driver for VCSELs (Vertical Cavity Surface

Emitting Laser) with bias, modulation & automatic power control current

source, and high speed photo-detector circuit, TIA (Tran-Impedance

Amplifier) and analog receive signal strength indicator. Completed EIO

(Electrical Interface to Optical) board, 8 TX Laser Emitters and 32 Photo-

Detectors, optical interconnection bandwidth is 3.125 Gbps BER 1E-12, and

optical power diagnostic/alignment/

calibrate for 8 TX Laser drivers & 32 RX photo-detectors into the light-box

interconnection. Completed the high speed electrical loopback circuits

design on EIO board run up to 4.25Gbps. All were designed by using Mental

Graphics DS Designer. Completed Design SERDES I/O, BERT (Bit Error Rate

Tester) and 3.125 Gbit Data Serial Communication on the Lattice FPGA.

Working on PCIe Data Transaction on Lattice FPGA.

Hewlett Packard Company (Vancouver, Washington) May 2005 -

Sept. 2006

HARDWARE DESIGN ENGINEER,

Working on ASIC FPGA Design Tester for HP Business Printing System:

Completed I2C, HP Mccii Buses, PWM&Tach and SPI Slave Controller, working

on Ink Assist, Motion, Drop Detect MICCI2 Bus, GPIO Buses and Other Power

PC Buses. This chip will be built by OKI for high volume Gate Array ASICs

which used to control the high end Business Ink-Jet Printing System and

built the System Tester board for business printer by using Cadence

Allegro.

Polyvision Inc. (Beaverton, Oregon) Jan. 2005 -

May 2005

TEST DEVELOPMENT ENGINEER,

Completed short-term contract to design and develop two test fixtures: the

analog & digital circuit design in the ultrasound, and infrared transmitted

& received systems that both test circuits are able to detect the different

signal strength level of ultrasound and infrared energy.

RadiSys Corp. (Hillsboro, Oregon) Dec. 2004 - Jan.

2005

ANALOG DESIGN ENGINEER,

Completed short-term contract for analog and digital board level design,

checked, measurement and calculated all the detail circuitry on board.

Completed to build the part list of the Electronic Derating for Optimum

Performance in order meet Agilent long term requirement. Suggested to

change the circuit design to meet the reliability requirement of Electronic

Derating for Optimum Performance.

DieBold, Inc. (North Canton, Ohio) 2002 - March

2004

SENIOR ELECTRONIC SYSTEMS ENGINEER,

Completed FPGA ASIC Design for IDM Product (Intelligence Deposit Machine)

for ATM: ARM7 & C515 micro-controller interface, stepper controller, sensor

interface, clock controller, PWM controller, optical scan interface,

magnetic scan interface, SPI controller, solenoid controller, ADC

interface, and impact & inkjet printer controller.

Completed Magnetic Scanner Design for magnetic documents: analog circuits,

analog board, mixed signal design, and calibrated & diagnostic circuit &

firmware design.

Completed FPGA ASIC Design for Advanced IDM Product, E13-B&CMC-7 Hardware &

Algorithm MICR scanner Design: analog, mixed circuits & digital circuits

design, layout, test plan, algorithm/software recognition design, and

double detected CMC-7 FPGA Controller.

Completed the Magnetic Imaging Scanner and USB Double Side Optical Scanner

for Advanced IDM Product.

All products above were completed Design Phases: Theory Operation,

Schematics, FPGA ASIC VHDL Code & Synthesis, Prototype Boards, Signal

Analysis, Design Testing, Debug and Release to Production.

IMS (Integrated Measurement Systems), Inc. (Beaverton, Oregon)

2001 - 2001

SENIOR HARDWARE DEVELOPMENT ENGINEER,

Completed research and design the new technology in development Rigel

TestBoard (14" x 16"): high speed LVDS buses, 420MHz clock transmission and

DDR (Double Data Rate) Synchronous Transaction from 840 Mb/s (1 LVDS bus)

to 38.82 Gb/s (48 LVDS buses), high speed VHDM & VHDM-HSD Teradyne

Connectors, Xilinx Virtex-II FPGA (XC2V1000 FF896) and Verilog-HDL codes

(Timing Simulation, Synthesis, and Xilinx Virtex-II FPGA JDEC files). High

speed Pipeline SRAM FPGA Double-Sided Mirror-Imaged for 18 & 36-Data bits,

and ECL-PECL-LVDS Bus Translators, LVDS Clock Distribution Circuitry &

Layout. Executed Test Plan on the High Speed Board and Signal Integrity:

Flight Time, Skew, Jitter & Signal Noise and BER (Bit Error Rate) of Single

& Multiple LVDS Buses. Wrote the Verilog-HDL for BER Testing and Checking

for High Speed Single & Multiple LVDS Bus Transaction.

Hewlett Packard Company (Vancouver, Washington) 1998 -

2001

PRODUCT DEVELOPMENT ENGINEER,

Worked R&D in Digital ASIC Chip, Main/Logic PCA Design, ESD, tracked Logic

PCA defect and helped solve those problems. Contributed to the debug and

resolution of Logic PCA defects that were captured during End of Day

meetings and other test lab for LP2/3/3.5/4/LVB/PP/MR, and found bad

components (Analog and Digital ASIC chips) with different suppliers

(wrong/bad parts and processing problems). Tested USB power sequencing

problems of Helios digital ASIC rev B2/3/4, and C2 on two suppliers (HP-

ICBD and Motorola). Interfaced with ICBD on Helios designing, testing and

problem solving related to defective Digital & Mixed ASIC during design

phase. Trained product engineers, solved many of EE issues in Broadway LVB

build and set up PCA Failure Analysis Station at HP-Singapore. Leaded

design to complete to save 1.50 dollars per Broadway Main PCA unit

(Circuitry and Solita Digital ASIC Chip). Completed EE design PathFinder,

and Alddin Fold Apart Tester. Took full responsibility for Digital ASIC

chip rev. B, C, Solita & Helios, and EE Product Signal Integrity (prevent

problems of EMI, ESD & Reliability) in Product Development Team.

Worked in the new design technology team: VIP (Vancouver Image Pipeline),

IR (Infrared), IEEE 1284 Bitronics, USB, IEEE 1394 Firewire, New LIO Buses

(LVDS), Bluetooth System and Micro-controller.

INTEL Corporation (Hillsboro, Oregon) 1995 -

1998

SENIOR DESIGN ENGINEER,

Developed Heceta Mixed ASIC Chip, emulator board, FAT Board and integrated

software (AHDL & VHDL). Developed Test Plan for Heceta Chip, executed Test

Plan on Heceta Chip, Debug Mixed ASIC issues and placed on central server

(George), evaluated Heceta Chassis Intrusion circuit, current draw, and

sensitivity. Determined Power Droop and Drop on USB and recommended

improvements. Got Fab C schematic, layout, BOM for Newport Motherboard in

preparation for doing Phase 0, and executed Phase 0 and placed results on

central server (George). As Dublin (DB440FX) Motherboard DE: Designed

Ethernet (ICS1890) and Wake On LAN (WOL) subsystems, low cost voltage

regulator module, and Riser card; Held design review on Super I/O PC87307,

PIIX3/4, USB and Ethernet & WOL. As Lead DE in Livermore worked on

Motherboard Development (First NET-PC Intel&IBM 440LX) with Pentium II

Processor. Developed and built 100 Base-TX and 10 Base-T IEEE 802.3 Test

Fixture for Ethernet PRO100M Controller. Worked on High Speed Signal

Integrity of Single End and Differential Signal Buses: GTL. PCI, ISA, USB,

IEEE-1394, LAN (TTL, CMOS, Skew Jitter & Noises, Motherboard Division

Design in House BER Software Testing and Bit Error Rate Debug &

Checking Full responsibility in supporting LAN design for Intel

Motherboard Division. As Hardware & Software Evaluation Engineer, had

responsibility for Hardware BIOS Hurlde Testing of Intel Alder System (Fab.

1 & 2) with three different operating systems: Windows NT Server &

Workstation 3.51, NetWare 4.10 & 4.10 SMP, UnixWare 2.02. Worked on Alder

System & main board debug, Orion ChipSet P6REGEDT Software test, debug &

verify. Set up Benchmark Alder System Performance Tests: NetBench 4.0 NT

3.51 and NetWare 4.10 & 4.10 SMP, ServerBench 2.0 NetWare 4.10 & 4.10 SMP,

PCBench 9.0 and WinBench 1.0.

ATALLA TANDEM Company (San Jose, California) 1993 - 1994

TEST ENGINEER,

Assistant in R&D Engineering Lab. had responsibility for building the test

procedure, writing C- and Assembly Languages to test, debug, and solve the

hardware problems of the first 100 prototypes ATALLA units (ACTT, ACH &

Mechanism).

CORPORATE SYSTEMS CENTER (Sunnyvale, California) 1991 - 1993

Technical Service and Support Test.

Designed and took care of projects CSC FASTCACHE 64 Harddisk Controller

SCSI & IDE in hardware and software, wrote C and assembly language to test

Maxoptics TAHITI 1, Maxtor hard drive (from 200MB to 1.7GB). Repaired the

used hard drive and customer return in clean room and did troubleshooting

on hard drive PCB controller: Maxtor, Conner Peripheral, Hewlett-Packard,

Micropolis, Quantum, Seagate, Fujitsu and so on.

COLORPREP Inc. (Redwood City, California) 1989 -

1991

HARDWARE DESIGN ENGINEER

Imaging & Graphing Systems, developing Scanner, Composer and Output Film

Systems. Team work with Graphics & Color Adjust Algorithm in C-Languages

for Optronics Scanner Projects and designed high resolution Video

Controller card. Responsibility for product, test, installation, quality

assurance, and maintenance Pre-Press Graphics Systems.

QUALOGY Inc. (Milpitas, California) 1988

-1989

HARDWARE/SOFTWARE TEST ENGINEER

Wrote C and assembly language to test IBM PC XT/AT 286 &386 single

motherboard, I/O, EGA & VGA graphics, hard disk & floppy controller, modem

card and DEC system controller board and multibus board.

PORTLAND STATE UNIVERSITY 1985 - 1987

E.E. Dept. Teaching assistant and collaborated with professor Chung Yu Wu

on High Speed VLSI Circuits Modeling and Simulation Program Design.

COURSE WORK, CONTINUED EDUCATION and SEMINARS:

Advanced VLSI Circuits Design * High Speed Signal Analysis & Design *

Advanced Analog and Digital Integrated Circuits Design * System Electronics

Design * VLSI Processing * CMOS VLSI Modeling * ASIC and Programmable Logic

Design * Digital System Engineering * Parallel and Distributed Architecture

* Advanced Computer Architecture Systems * Memory Systems * Microprocessor

& Multiprocessor System Design * I/O Interfacing Design & Applications *

Data Communication * Switching Theory * Advanced Digital Signal Processing

* Advanced Communication Theory * Software Design * Computational Methods

and Research Tools in Electrical Engineering (Non-Linear Optimization

Programming) * Analog & Digital Modern Control Systems * Optical

Electronics * Operating System UNIX (C-Languages & C SHELL Programming) *

Instrumentation Systems * Seminars: EMC, ESD, Signal Integrity, ASIC

Project Planning, Intel/PC Architecture, LAN Design & Testing, LVDS I/O

High Speed Circuit Design, High Speed On/Off-Chip Design, On/Off-Chip

Thermal Design, On Chip Testing and Digital communication.

EDUCATION

Master of Science in Electrical Engineering, Portland State University

1987

Bachelor of Science in Electrical Engineering, Portland State University

1985

PERSONAL: U.S. Citizen

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