| Resume alert | Resumes 41 - 50 of 386 |
Digital and Physical Design Engineer, Verification Engineer
Santa Clara, CA
... HSPICE, Xilinx Vivado, PrimeTime(STA), Innovus(PnR), Design Compiler(Synthesis) Verification Methodologies: UVM (basics), FPGA Prototyping, Formal Verification, Assertion based Verification Other: ABC Synthesis Tool, AutoCAD, SAL, SPIN, MS Office, ... - 2021 May 30
... HSPICE, Xilinx Vivado, PrimeTime(STA), Innovus(PnR), Design Compiler(Synthesis) Verification Methodologies: UVM (basics), FPGA Prototyping, Formal Verification, Assertion based Verification Other: ABC Synthesis Tool, AutoCAD, SAL, SPIN, MS Office, ... - 2021 May 30
iOS Developer
San Jose, CA
... Complete, verify and deliver FPGA on schedule. FPGA successfully works with the client's MEMs display. Define the micro-architecture, implement the behavioral models, verify functional blocks, debug and verify thoroughly the design against defined ... - 2021 Mar 03
... Complete, verify and deliver FPGA on schedule. FPGA successfully works with the client's MEMs display. Define the micro-architecture, implement the behavioral models, verify functional blocks, debug and verify thoroughly the design against defined ... - 2021 Mar 03
Engineering Engineer
San Jose, CA
... at University of Massachusetts, 2017-2021 Lecturer at University of Massachusetts for Probability and Statistics, 2019 FPGA Architecture Intern at University of Massachusetts, 2016-2017 Test and Veri cation Intern at University of Massachusetts, ... - 2021 Jan 06
... at University of Massachusetts, 2017-2021 Lecturer at University of Massachusetts for Probability and Statistics, 2019 FPGA Architecture Intern at University of Massachusetts, 2016-2017 Test and Veri cation Intern at University of Massachusetts, ... - 2021 Jan 06
Electrical Engineering Student
Santa Clara, CA
... statements for components Assembly: Utilizing STM Discovery boards and ARM to program keypad, addressable LEDs, ADC/DAC converters, understanding stacks/recursion/pointers in Assembly FPGA/Verilog: Creating component blocks in Quartus Prime (ex. ... - 2020 Dec 23
... statements for components Assembly: Utilizing STM Discovery boards and ARM to program keypad, addressable LEDs, ADC/DAC converters, understanding stacks/recursion/pointers in Assembly FPGA/Verilog: Creating component blocks in Quartus Prime (ex. ... - 2020 Dec 23
Application Engineer II
Sunnyvale, CA
... Pipelining, Cache •Knowledge on ASIC Design flow - RTL, Synthesis, Simulation, Custom Layout, Logic Equivalence Checking (LEC), Floor Planning, Placement and Routing, Design Compiler Synthesis flow, FPGA Design flow, FPGA Prototyping. SKILLS •EDA ... - 2020 Dec 21
... Pipelining, Cache •Knowledge on ASIC Design flow - RTL, Synthesis, Simulation, Custom Layout, Logic Equivalence Checking (LEC), Floor Planning, Placement and Routing, Design Compiler Synthesis flow, FPGA Design flow, FPGA Prototyping. SKILLS •EDA ... - 2020 Dec 21
Director of Program Management
San Jose, CA
... Hiring and management of a team of 10+ engineers, including ATE, hardware, FPGA, mechanical and PCB design Led the product development process from architecture and specifications through customer shipment within 1 year As Interim Director System ... - 2020 Dec 20
... Hiring and management of a team of 10+ engineers, including ATE, hardware, FPGA, mechanical and PCB design Led the product development process from architecture and specifications through customer shipment within 1 year As Interim Director System ... - 2020 Dec 20
Design Engineering
San Jose, CA
... • Assisted and mentored students in Lab assignments based on Vivado HLS and Basys 3 FPGA. In-plant Trainee, Bharat Electronics Limited, India Nov 2016 - Dec 2016 • Gained knowledge on Development and Engineering department that monitors the tank ... - 2020 Dec 10
... • Assisted and mentored students in Lab assignments based on Vivado HLS and Basys 3 FPGA. In-plant Trainee, Bharat Electronics Limited, India Nov 2016 - Dec 2016 • Gained knowledge on Development and Engineering department that monitors the tank ... - 2020 Dec 10
Engineer Electrical
Livermore, CA
... FPGA design; DFT; DFM; DFC; Implement Multi-chip modules and bonding Flip-chip solder in micro BGA; Design of flip-chip process using copper pillars bump. - Experience of Circuit stability with feedback loop optimization; RF Impedance matching; ... - 2020 Nov 28
... FPGA design; DFT; DFM; DFC; Implement Multi-chip modules and bonding Flip-chip solder in micro BGA; Design of flip-chip process using copper pillars bump. - Experience of Circuit stability with feedback loop optimization; RF Impedance matching; ... - 2020 Nov 28
Python Data
Santa Clara, CA, 95054
... to control the speed and position of servo actuator in the launch vehicle, which is based on a BLDC motor and the whole system was implemented in FPGA EDUCATION M.S., Electrical Engineering (3.75/4.00) San Jose State University, USA Dec 2020 B. ... - 2020 Nov 18
... to control the speed and position of servo actuator in the launch vehicle, which is based on a BLDC motor and the whole system was implemented in FPGA EDUCATION M.S., Electrical Engineering (3.75/4.00) San Jose State University, USA Dec 2020 B. ... - 2020 Nov 18
Sholeh Gregory Technical Writer Security
Livermore, CA
... Altera Corporation, San Jose, CA 12/04 – 1/05 Contract Senior Technical Writer, Engineering Division Increased the usability of an application note about a design security feature embedded into an FPGA device, which decrypted a configuration bit ... - 2020 Oct 31
... Altera Corporation, San Jose, CA 12/04 – 1/05 Contract Senior Technical Writer, Engineering Division Increased the usability of an application note about a design security feature embedded into an FPGA device, which decrypted a configuration bit ... - 2020 Oct 31