| Resume alert | Resumes 1 - 10 of 17 |
Verilog coding
Visakhapatnam, Andhra Pradesh, India
... 2016, visakhapatnam, 65% SKILLS verilog coding basics of c programming c++ Basics of java and python commuication skills problem solving team work can work under stressed conditions basic computer knowledge time management can handle cadence,linux. ... - 2023 Sep 11
... 2016, visakhapatnam, 65% SKILLS verilog coding basics of c programming c++ Basics of java and python commuication skills problem solving team work can work under stressed conditions basic computer knowledge time management can handle cadence,linux. ... - 2023 Sep 11
Control Systems Fpga Design
Visakhapatnam, Andhra Pradesh, India
... Secondary Education, AP 10th grade (2014) CGPA - 7.0 Specializations Areas of interest Technical Skills: Digital Circuits,Verilog Verilog,Cadence,C,Ptyhon(basics) ASIC, FPGA, Cadence(RTL-GDS) Simulation Software: Cadence Virtuoso, TopSpice, Xilinx ... - 2023 Sep 11
... Secondary Education, AP 10th grade (2014) CGPA - 7.0 Specializations Areas of interest Technical Skills: Digital Circuits,Verilog Verilog,Cadence,C,Ptyhon(basics) ASIC, FPGA, Cadence(RTL-GDS) Simulation Software: Cadence Virtuoso, TopSpice, Xilinx ... - 2023 Sep 11
Internship Telecom
Visakhapatnam, Andhra Pradesh, India
... PROJECT: Project Name: Implementation Of Orthogonal Frequency Division Multiplexer (OFDM) Using Fast Fourier Transform (FFT) And Inverse Fast Fourier Transform (IFFT) In Verilog Programming Language Project Description: To Improve The Speed Of ... - 2021 Jul 10
... PROJECT: Project Name: Implementation Of Orthogonal Frequency Division Multiplexer (OFDM) Using Fast Fourier Transform (FFT) And Inverse Fast Fourier Transform (IFFT) In Verilog Programming Language Project Description: To Improve The Speed Of ... - 2021 Jul 10
Office Engineering
Visakhapatnam, Andhra Pradesh, India
... (Intermediate) VHDL & Verilog Declaration I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above-mentioned particulars. Date : Place : (Mahesh Siripurapu) - 2021 Mar 31
... (Intermediate) VHDL & Verilog Declaration I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above-mentioned particulars. Date : Place : (Mahesh Siripurapu) - 2021 Mar 31
Engineering Assistant
Visakhapatnam, Andhra Pradesh, India
... PUC Rajiv Gandhi University of Knowledge Technologies, Nuzvid 2014-2016 8.92 Distinction SSC Z.P.H.S JALLURU 2014 9.8 Distinction Technical Skills: Programming languages: Basic C language, JAVA,Basic PYTHON,VERILOG,ASSEMBLY,MATLAB,AURDINO. ... - 2021 Feb 15
... PUC Rajiv Gandhi University of Knowledge Technologies, Nuzvid 2014-2016 8.92 Distinction SSC Z.P.H.S JALLURU 2014 9.8 Distinction Technical Skills: Programming languages: Basic C language, JAVA,Basic PYTHON,VERILOG,ASSEMBLY,MATLAB,AURDINO. ... - 2021 Feb 15
Design Assistant
Visakhapatnam, Andhra Pradesh, India
... Experience in test bench development in both VHDL/Verilog and its interface with DUT Self -starter, enthusiastic and leading a team. A highly motivated and strategically focused performer An effective, innovative professional with strong analytical ... - 2020 Dec 14
... Experience in test bench development in both VHDL/Verilog and its interface with DUT Self -starter, enthusiastic and leading a team. A highly motivated and strategically focused performer An effective, innovative professional with strong analytical ... - 2020 Dec 14
Manager Python
Visakhapatnam, Andhra Pradesh, India
... Certified in SystemOnChip Verification Using System Verilog Language. Certified in Python Programming. Having hands-on experience using Python programming language with Classes,Objects,OOPS concepts, Numpy, Pandas. Hands-on experience using machine ... - 2020 Nov 26
... Certified in SystemOnChip Verification Using System Verilog Language. Certified in Python Programming. Having hands-on experience using Python programming language with Classes,Objects,OOPS concepts, Numpy, Pandas. Hands-on experience using machine ... - 2020 Nov 26
Engineering Customer
Visakhapatnam, Andhra Pradesh, India
... 17 89 3 SSC Oxford Concept School STATE BOARD 2014 93 TECHNICAL SKILLS: Programming language: C,basics of Java Packages: Verilog Operating System: MSDOS Certification: Completed PSS course through NPTEL Secured prize for distinctive and outstanding ... - 2020 Oct 14
... 17 89 3 SSC Oxford Concept School STATE BOARD 2014 93 TECHNICAL SKILLS: Programming language: C,basics of Java Packages: Verilog Operating System: MSDOS Certification: Completed PSS course through NPTEL Secured prize for distinctive and outstanding ... - 2020 Oct 14
Engineering Digital
Visakhapatnam, Andhra Pradesh, India
... Verilog VLSI programming 3. MATLAB for Signal Processing 4. I have knowledge on LabVIEW, OrCAD pspice, Basics of Embedded C, Linux – Ubuntu and SOC. Internships and training: 1. Internship on Telemetry at DRDL in May 2018. 2. Internship as a HR at ... - 2020 Aug 04
... Verilog VLSI programming 3. MATLAB for Signal Processing 4. I have knowledge on LabVIEW, OrCAD pspice, Basics of Embedded C, Linux – Ubuntu and SOC. Internships and training: 1. Internship on Telemetry at DRDL in May 2018. 2. Internship as a HR at ... - 2020 Aug 04
Air Force Engineer
Visakhapatnam, Andhra Pradesh, India
... International Paper IJARCCE (Published a research paper entitled Low Power FinFET Based Full Adder Design) Volume 6, Issue 8, August 2017 AFFILIATION SKILLS C, C++, CADENCE, DIGITAL ELECTRONICS, Verilog HDL OPERATING SYSTEMS MS Office, Access, Power ... - 2020 Jul 15
... International Paper IJARCCE (Published a research paper entitled Low Power FinFET Based Full Adder Design) Volume 6, Issue 8, August 2017 AFFILIATION SKILLS C, C++, CADENCE, DIGITAL ELECTRONICS, Verilog HDL OPERATING SYSTEMS MS Office, Access, Power ... - 2020 Jul 15