Vamsi Prasad Mirthinti

**-*-*/*, ******* Road,

Gajuwaka, Visakhapatnam 530026

adel0m@r.postjobfree.com

738-***-****

**-**-****

CARRER OBJECTIVE To become a successful professional by building a career with leading corporate having challenging & creative environment, which will help me to explore myself fully and realize my potential and thereby to be a part of Organization's success.

WORKING EXPERIENCE

COMPANY: CONSTRUCTION DEVELOPMENT COMPANY INTERNATIONAL PRIVATE LIMITED

ROLE: SAP CMMS ENGINEER

TENURE: FROM FEBRUARY 2018 TO TILL DATE

ACTIVITIES INVOLVED

FMTL PREPARATION

SPARE PARTS LIST & INTERCHANGE ABILITY RECORDS (SPIR)

DOCUMENT MASTER

HERARCHY

SITE VALIDATION REPORT PREPARATION

MTL PREPARATION

CLIENTS

QATAR KENTZ

DUKHAN

GALFAR

ALMUFTAH

AL BALAGH

RAS-LAFFAN

DESCRIPTION

Verify the equipment’s by using P&ID, Single Line Diagrams & Layout Diagrams (F&G,

Telecommunication & HVAC).

Preparing First Pass Master Tag List.

Preparing Hierarchy Report and Bill of Materials.

Document Control Register & Document Master Preparation.

Mentioning some changes through submitted redline markup to prepare as-built diagrams.

Preparing project status report to clients

Preparing Site validation report and capturing all the data for asset verification.

QUALIFICATION

BOARD

NAME OF THE COLLEGE/UNIVERSITY

PERCENTAGE

M.Tech(ECE)

Specialization: VLSI Design and Embedded Systems

JNTU Kakinada

GAYATRI VIDYA PARISHAD COLLEGE OF ENGINEERING

71

CGPA:7.8

B.Tech(ECE)

GITAM UNIVERSITY

GITAM UNIVERSITY

73.2

CGPA: 7.32

INTERMEDIATE

STATE BOARD

SRI CHAITANYA JUNIOR COLLEGE

81.4

SSC

STATE BOARD

SFS SCHOOL

78.3

EDUCATIONAL

QUALIFICATION

.

M.Tech Project Low Power FinFET Based Full Adder Design

The great challenge in the nanometer regime is due to short channel effects that causes an exponential increase in the leakage current. With the advancement in technology, conventional CMOS has short channel Effect. In order to overcome these short channel effects FinFET is used. FinFETs are the new emerging transistors that can work in the nanometer range to overcome these short channel effects. The project is to implement low power FinFET base Full Adder using 45nm with the supply voltage of 1V for CMOS and GDI CMOS using 15nm technology with the supply voltage of 0.7V for FinFET and GDI FinFET. The simulation is used to compare Delay, Power and Power-Delay Product.

B.Tech Project FM Transmitter with Audio Modulation

The project's goal is to create an FM transmitter, which transmits, it redundancy, a signal or sound to an FM receiver, without the need for cables. We opted this project as it is related to communication and our batch-mates want to pursue their higher education in communication field. This project can also be used in army, navy and also in air force for communication purposes. This project can also be further developed and can be used for secured data transmission which has many wide uses in every communication sector of our country.

International Paper IJARCCE (Published a research paper entitled Low Power FinFET Based Full Adder Design)

Volume 6, Issue 8, August 2017

AFFILIATION SKILLS C, C++, CADENCE, DIGITAL ELECTRONICS, Verilog HDL

OPERATING SYSTEMS MS Office, Access, Power Point and Excel

Expert in working on SAP IDB Database using Microsoft Access and Excel.

Expert in designing using software tools like cadence using 45nm technology and NCSU_Techlib_Free PDK 15nm technology.

Expert in Installing FinFET library files in CADENCE Virtuoso Tool using code language files.

Member of IETE and IEEE

ACHIEVEMENTS Runner up in Volley Ball Game held in School Tournament

Achieved Certificate on Madhyama School Level Exam with First Class

Achieved Publication Certificate on submitting research paper at IJARCCE (International Journal)

Extracurricular Activities Attended IOT (Internet of Things) Work Shop held in Gayatri Vidya Parishad College of Engineering

Presented Paper on Android Systems at Gitam University

Participated in IETE Carnival 2013

Presented many Project Reviews on Low FinFET Based Full Adder Design at Gayatri Vidya Parishad College of Engineering.

HOBBIES Watching Cricket

Listening to Music

Bike Riding

Declaration I hereby declare that the above information is correct up to my knowledge and I bear the responsibility for the correctness of the above mentioned particulars

Vamsi Prasad Mirthinti

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