Office Engineering

Mahesh Siripurapu

Chinna Veddhi,

Korukonda,

Vizianagaram,

Andhra Pradesh, 535214

Email: ******.**************@*****.***

LinkedIn-www.linkedin.com/in/mahesh-siripurapu-ba8b89176

Mobile : +919*********, +918*********

Career Objective

To excel and work in a highly competitive environment with a perfect challenge by contributing the best for the growth of the organization while ensuring growth in personal career.

Academic details

Degree/Course

University/Board

Year of Passing

Percentage

/ CGPA

B.Tech

( Electronics and Communication Engineering )

JNTUK

(Raghu Institute of Technology)

2021

8.0

( Up to VIth Sem)

Intermediate

(10+2) (M.P.C)

AP Board of Intermediate Education

(Sri Chaitanya Junior College-VSKP)

2017

9.1

SSC

AP Board of Secondary Education

2015

9.5

Achievements

Received PRATIBHA award from Govt. AP in 10th standard for best in academic results

Secured second place in IOT Challenge 2019 held at IIT – Bombay

Participated in District Level Inspire Science Exhibition- 2012 behalf of Govt. High School

Participated in state level science exhibition and project compilation 2013- JNTUA

Project Performed

Title : Hand Free Navigator

Description : Implemented the new navigation based driving technology for benefit of the driver rather than Google navigation flexibility to bulid smart & hand free navigator with help of known short direction drivers.Most helpfull for two wheelrs riders, when both hands are occupied while driving.

Trainings, Workshops attended and Certificate Course

Attended the three days workshop on IOT boot camp held at RIT-VSK

One day industrial visit and training at district central BSNL office -VSKP

Participated in Section Student Congress – 2019 organized by IEEE held at JNTUH

Professional body Memberships

IEEE membership with enrolment id - 95551901

IETE membership

Strengths

Possess Positive attitude

Ability to work under high pressure

Responsible towards work

Quick Learner

Software Knowledge

C Programming

PYTHON (Intermediate)

VHDL & Verilog

Declaration

I hereby declare that the above-mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above-mentioned particulars.

Date :

Place : (Mahesh Siripurapu)

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