| Resume alert | Resumes 1 - 10 of 67 |
Mini Project Engg
Pune, Maharashtra, India
... TECHNICAL SKILLS: DESIGNING SOFTWARES KNWOLEDGE: NI Multisim Xilinx & Proteus PROGRAMING SOFTWARE KNOWLEDGE: C LANGUAGE, DATA STRUCTURE, MATLAB, FPGA, NI LABVIEW, Assembly Language: 8051, Embedded C, Python, VHDL, Verilog. PROJECTS: Designed ... - 2021 Dec 07
... TECHNICAL SKILLS: DESIGNING SOFTWARES KNWOLEDGE: NI Multisim Xilinx & Proteus PROGRAMING SOFTWARE KNOWLEDGE: C LANGUAGE, DATA STRUCTURE, MATLAB, FPGA, NI LABVIEW, Assembly Language: 8051, Embedded C, Python, VHDL, Verilog. PROJECTS: Designed ... - 2021 Dec 07
C, Python, Verilog, Quality Assurance, Testing
Pune, Maharashtra, India
... TECHNICAL SKILLS: 1) Programming: Verilog HDL, Python 3, C 2) Tools: Xilinx ISE Design Suite 14.7, Xilinx Vivado, JIRA, Ellisys Bluetooth Analyzer, PCB Designing using Lab center Proteus Professional 8, BlueZ Stack, Frontline Analyzer, Arduino UNO. ... - 2021 May 20
... TECHNICAL SKILLS: 1) Programming: Verilog HDL, Python 3, C 2) Tools: Xilinx ISE Design Suite 14.7, Xilinx Vivado, JIRA, Ellisys Bluetooth Analyzer, PCB Designing using Lab center Proteus Professional 8, BlueZ Stack, Frontline Analyzer, Arduino UNO. ... - 2021 May 20
Mysore Trainee
Pune, Maharashtra, India
... TECHNICAL SKILLS: • Power electronics • Vhdl and verilog • Digital and analog electronics • Basic knowledge of C,C++, Python INTERNSHIPS : • Python Programming conducted by V S Technologies, Mysore. • PCB design at Hamshine electronics, Hassan. ... - 2021 May 13
... TECHNICAL SKILLS: • Power electronics • Vhdl and verilog • Digital and analog electronics • Basic knowledge of C,C++, Python INTERNSHIPS : • Python Programming conducted by V S Technologies, Mysore. • PCB design at Hamshine electronics, Hassan. ... - 2021 May 13
Assistant Python
Pune, Maharashtra, India
... LinuxOS AdobeSuite MATLAB MicrosoftOffice365 AltiumDesigner ArduinoIDE Eclipse CodeComposerStudio MPlabIDE XiLINX VHDL/Verilog ENGINEERING/TECHNOLOGY Languages:– MATLABProgramming HTML Java JavaScript Linux Python PHP C,C++ WebServers:– Node.JS ... - 2021 Mar 13
... LinuxOS AdobeSuite MATLAB MicrosoftOffice365 AltiumDesigner ArduinoIDE Eclipse CodeComposerStudio MPlabIDE XiLINX VHDL/Verilog ENGINEERING/TECHNOLOGY Languages:– MATLABProgramming HTML Java JavaScript Linux Python PHP C,C++ WebServers:– Node.JS ... - 2021 Mar 13
Project Engineering
Pune, Maharashtra, India
... Languages: C, C++, OOP, Python, Verilog, SystemVerilog, UVM • Development and Simulation Tools: Cadence, Xilinx ISE, Orcad 99SE, Keil μVision, NGspice, Proteus, MATLAB • Worked as a Project Intern in the domain of VLSI with ESCICOMP-INDIA PVT. ... - 2021 Mar 11
... Languages: C, C++, OOP, Python, Verilog, SystemVerilog, UVM • Development and Simulation Tools: Cadence, Xilinx ISE, Orcad 99SE, Keil μVision, NGspice, Proteus, MATLAB • Worked as a Project Intern in the domain of VLSI with ESCICOMP-INDIA PVT. ... - 2021 Mar 11
Engineer Project
Pune, Maharashtra, India
... I have basics knowledge about of programs VHDL and Verilog codes in Xilinx software tool. EDUCATION BE (E&TC) – Shivaji University, Kolhapur (Maharashtra) - 2018 Diploma (E&TC) – Dr. A. D. Shinde Institute of technology, Gadhinglaj (Maharashtra) ... - 2021 Feb 15
... I have basics knowledge about of programs VHDL and Verilog codes in Xilinx software tool. EDUCATION BE (E&TC) – Shivaji University, Kolhapur (Maharashtra) - 2018 Diploma (E&TC) – Dr. A. D. Shinde Institute of technology, Gadhinglaj (Maharashtra) ... - 2021 Feb 15
Engineering Information
Pune, Maharashtra, India
... 5 Verilog Language 6 Visual studio 7 Matlab 8 Xilinx 9 Microcontroller Personal details: Father’s name - Ranjit Purushottam Rode Date of Birth - 17 June 1999 Permanent address - At Bembala bk, post khallar Language Known - English, Hindi, Marathi. ... - 2021 Feb 14
... 5 Verilog Language 6 Visual studio 7 Matlab 8 Xilinx 9 Microcontroller Personal details: Father’s name - Ranjit Purushottam Rode Date of Birth - 17 June 1999 Permanent address - At Bembala bk, post khallar Language Known - English, Hindi, Marathi. ... - 2021 Feb 14
Engineering Safety
Pune, Maharashtra, India
... TRAINING VLSI designing (Verilog) summer training for 1 month in Hyderabad. Industrial Automation for six days. SEMINAR PRESENTED Seminar presented on “3D FPGA VS MULTIPLE FPGA” in Bachelor of Engineering in Electronics and Telecommunication held at ... - 2021 Feb 13
... TRAINING VLSI designing (Verilog) summer training for 1 month in Hyderabad. Industrial Automation for six days. SEMINAR PRESENTED Seminar presented on “3D FPGA VS MULTIPLE FPGA” in Bachelor of Engineering in Electronics and Telecommunication held at ... - 2021 Feb 13
Design Engineer
Pune, Maharashtra, India
... HDL Programming : Verilog(Xilinx ISE Design Suite). Microcontroller Programming : 8051, UART, I2C, SPI programming. Linux Programming : Basics of Linux, Socket programming, Basics of Networking, Docker. Other Tool’s : Matlab, Octave. >>Area Of ... - 2021 Feb 12
... HDL Programming : Verilog(Xilinx ISE Design Suite). Microcontroller Programming : 8051, UART, I2C, SPI programming. Linux Programming : Basics of Linux, Socket programming, Basics of Networking, Docker. Other Tool’s : Matlab, Octave. >>Area Of ... - 2021 Feb 12
Design Engineer
Pune, Maharashtra, India
... LANGUAGES : C Language,Verilog,System Verilog, C++, Python. ACADEMIC PROJECTS: 1.Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes Acadmeic Projects. Crafted and executed chip development ... - 2021 Feb 12
... LANGUAGES : C Language,Verilog,System Verilog, C++, Python. ACADEMIC PROJECTS: 1.Low-Power 19-Transistor True Single-Phase Clocking Flip-Flop Design Based on Logic Structure Reduction Schemes Acadmeic Projects. Crafted and executed chip development ... - 2021 Feb 12