Prachi Dnyaneshwar Kulkarni

c/o: Talegaon dabhade, Pune,

Near to Indrayani College

Phone: <+91-705*******>

<+91-957*******>

Email: adkudl@r.postjobfree.com

Career Objective

To become knowledge key for organization by consistently exceeding skills through hard work, creativity, innovation, determination and the effective utilization of system thinking. Academic Qualification

Pursued M. Tech. (2017-2019) in Electronics and Telecommunication Engineering with specialization

'VLSI and Embedded Systems' at College of Engineering, Pune Class Year College/University CGPA/Percentage

M.Tech.

(VLSI & Embedded

Systems)

2017-2019

College of Engineering,

Pune

7.00

B. E. (E&TC)

2012-2015

Fabtech College of Engineering

and Research, Sangola

78.13%

Diploma(E&TC)

2009-2012

Shivaji Polytechnic College,

Sangola

78.40%

S.S.C

2008-2009

Pune Board

72.73%

Professional Skill Set

• Operating system:

Windows XP, 2007, 2008, Linux

• Programming Languages:

C, C++, OOP, Python, Verilog, SystemVerilog, UVM

• Development and Simulation Tools:

Cadence, Xilinx ISE, Orcad 99SE, Keil μVision, NGspice, Proteus, MATLAB

• Worked as a Project Intern in the domain of VLSI with ESCICOMP-INDIA PVT. LTD, Pune from June 2018 to June 2019

• Worked as a Trainee Engineer in the domain of Electrical with AG Electro Services, Karad from 2015-17

• Knowledge of Cortex M3 Processor and OOPS concepts

• Having good knowledge of Verilog, System Verilog and UVM.

• Having good Knowledge of Computer Networking.

• Excellent team player with Hardware designing & Verilog coding skill Experience Summary

Academic Projects

This project is developed during the M.Tech Academic year and the project is sponsored by ESCICOM INDIA PVT. LTD, Pune

Project Name SV-UVM based Ethernet MAC UVC Development Period June 2018 to June 2019

Number of students Individual

Project Type Development

Brief Description • In this project, a Universal Verification Component

(UVC) of the Ethernet MAC Protocol is developed

using System Verilog Universal Verification

Methodology (SV-UVM).

• The developed UVC uses the UVM Environment for

verifying functionality of the Ethernet MAC protocol.

• This project creates a soft IP for the verification purpose.

• This UVC can be reused in different applications for verification of IP.

• Thus here we have designed a dedicated UVC for

verifying other IPs using UVM, which improves the

test coverage and reused in the verification

environment

Role • Studied the Universal Verification Methodology (UVM) and Ethernet MAC Protocol

• Developed UVC for 10Gbps Ethernet

• Checked the performance of UVC

This projects is developed during the M.Tech (Mini- Project): Project Name Design of an ALU and Operand registers Block OpA, OpB, Offset, and Out will be a simple buffer for pipeline operation Number of students 3

Period One month

Project Type Design

Brief Description • ALU and Operand register block are designed in Verilog for Pipeline Operation using Xilinx ISE

Tool on Cadence.

• ALU is combinational digital circuit that performs arithmetic and bitwise operations on integer binary numbers

Role • Verilog coding of Operand registers blocks

• Verilog coding of ALU

Project Name Design a Sense Amplifier for reading the CMOS SRAM cell Number of students 3

Period One month

Project Type Design

Brief Description • Semiconductor memories are usually considered to be the most vital Microelectronics Component of digital design for mainframe computers, automotive and

military Avionics systems.

• The primary function of Sense amplifier in SRAM is to amplify a small analog differential voltage developed on the bit lines by a read accessed cell to the full swing digital output swing digital output signal.

• SRAM is a type of RAM that holds data in a static form

• CMOS SRAM is most popular SRAM cell due to its

superior robustness, low power and low power

operation.

• In this project, we studied read, write and standby operations of SRAM.

Role • Design of Sense Amplifier by Using Cadence Tool.

• Studied Read, Write and Standby operations of SRAM. This project is developed during the Bachelor of Engineering: Project Name GPS based Bus location displaying and announcement system

Period July 2014 to April 2015

Number of students 4

Project Type Microcontroller based Design

Brief Description • This project displays and announces the name of upcoming location of a bus with the help of GPS

technology.

• The signals sent by the satellites to a GPS receiver are interfaced with PC for locating the exact location of a bus.

• These receivers receive the signals from the satellites based on three-dimensional locations such as latitude, longitude, and altitude with precise time.

• These coordinate values are stored in the

microcontroller. These coordinates represent the bus or train locations.

• These coordinates’ values are compared with the

values from the GPS receiver. Then that coordinated values are equal to the latest coordinates coming from the GPS modem and are converted into TTL level

with the help of MAX 232.

• This project is very helpful for the blind people, illiterate people and People who are new to a city.

Role Hardware development and Assembly coding

This project is developed during Diploma (EnTC):

Project Name Automatic room light controller with Visitor counter Period June 2011 to June 2012

Number of students 4

Project Type Microcontroller based Design

Brief Description • This project does the task of controlling the room lights as well as Counting number of persons entered in the room using microcontroller 8051

• This project has two module, the first one is Digital visitor counter and second module is Automatic room light Controller.

• The Visitor counter which measures the number of persons entering any room and this function is

implemented using a pair of Infrared Sensors.

• The LCD display placed outside the room displays this value of person count.

Role Hardware development and Assembly coding

Technical Activities

• Workshop on “Processor Design using Cadence Tensilica Processor Platform” at COEP, 2018

• Symposium on "Information and Cyber Security Research", 2018

• CCNA Training at Proactive IT Services Ltd, Pune, 2016

• Workshop on Mechatronics conducted by IARE Technologies, 2015

• Vocational Training of MSEB at Pandharpur, 2014

• Vocational Training of BSNL at Solapur, 2012

Relevant Courses

• RTL Simulation and Synthesis with PLD (EVE-5002)

• VLSI Design Verification and Testing (EVE-15012)

• System Design with Embedded Linux (EVE-15011)

Achievements

• Won 1st prize in State level Paper presentation in ‘TECHNOFAB2K14’ held in FTC, Sangola

• Won 1st prize in sports badminton and carrom in Academic Year of B..E.

• Won 1st prize in singing in Academic year of B..E.

• Cultural and Sports coordinator of ETESA for the year 2011-12

• Actively participated in Badminton and carrom at Zonal level, 2011-12 Strengths and Interests

• Like to lead people and manage tasks

• Diplomatic

• Positive Attitude

• Good time management

Personal Details

Name : Prachi D. Kulkarni.

Father’s Name : Dnyaneshwar P. kulkarni.

Date of Birth : 12th May 1994.

Gender : Female.

Nationality : Indian.

Marital Status : Unmarried.

Permanent Address : Mahadev Galli, Sangola.

A/p-Sangola, Dist-Solapur.

Maharashtra.

Pin code-413307

Languages : English, Hindi, Marathi.

Declaration:

I hereby declare that the above mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above mentioned particulars.

(Prachi Kulkarni)

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