SAURAV SURI

MTech, Embedded System Design

701-***-**** admkub@r.postjobfree.com

OBJECTIVE:

To pursue a demanding career and continue pace with the ever changing requirements in the industry by acquiring new skills and awareness with the most up-to-date technologies. EXPERIENCE:

1) Software Quality Assurance Intern • NXP Semiconductors • JULY 2020 - JUNE 2021

• Working in Bluetooth-Core Team.

• Validation of Bluetooth Firmware and various BR/EDR-BLE Profiles like A2DP, HFP, HID, HOGP, GATT etc. is done by me.

• Good Knowledge of Bluetooth and Bluetooth Low Energy.

• Creating and Maintaining the Test Report.

• Analyzing and Debugging Over-the-Air Logs (Ellisys/Frontline Sniffer) and btmon/hcidump Logs of Failed Test Cases.

• Raising Software and Firmware bugs on Jira and Tracking it.

• Running various Automation scripts written in Perl for Bluetooth Profile Testing. 2) Quality Assurance Engineer • Mars electronics • Feb 2019 - Jul 2019 Quality Assurance of Various Scientific Instruments like DSO, CRO, multimeters, Digital and Analog Electronic Kits used in Colleges is done by me. TECHNICAL SKILLS:

1) Programming:

Verilog HDL, Python 3, C

2) Tools:

Xilinx ISE Design Suite 14.7, Xilinx Vivado, JIRA, Ellisys Bluetooth Analyzer, PCB Designing using Lab center Proteus Professional 8, BlueZ Stack, Frontline Analyzer, Arduino UNO. 3) Operating System:

Linux, Windows, Android GUI and Embedded Linux for NXP Chipsets. 4) Boards:

FPGA (Xilinx Spartan 3E and Zybo Z10), iMX8M (PCIE-UART, SD-SD, SD-UART) 5) BUS Protocols:

I2C, SPI

EDUCATION:

1) Master of Technology • 2019 - 2021 • NIT Kurukshetra Embedded System Design with current CGPA of 8.88

2) Bachelor of Technology • 2014 - 2018 • UIET Kurukshetra Electronics and Communication Engineering with a percentage of 67.40 3) Higher Secondary School • 2013 - 2014 • CBSE Board Non-Medical with a percentage of 89.40

4) Senior Secondary School • 2011 - 2012 • CBSE Board Passed with a CGPA of 9.2

PROJECTS:

1) Hardware Implementation of an Enhanced AES Algorithm using Verilog HDL • Single • Thesis

• Functional Verification: Behavioral Simulation of Individual AES Modules

• RTL Design: RTL Design using Verilog HDL + Xilinx Vivado

• FSM Design: Using sequential circuit for Individual rounds of AES (10 States)

• Pipelining: To optimize the design, Pipelining is used between data inputs of individual rounds. 2) I2C Protocol • Single

• Functional Verification: Behavioral Simulation of I2C Protocol

• RTL Design: RTL Design using Verilog HDL + Xilinx ISE Design Suite

• FSM Design

3) Complex Multiplier • 3 members

• Functional Verification: Behavioral Simulation of I2C Protocol

• RTL Design: RTL Design using Verilog HDL + Xilinx ISE Design Suite

• Data Path and Control Path Design

4) Vending machine • Single

• Functional Verification: Behavioral Simulation of I2C Protocol

• RTL Design: RTL Design using Verilog HDL + Xilinx ISE Design Suite

• FSM Design

5) Digital Lock • 2 members

• AVR based (ATMEGA-8) Keypad Lock.

• Arduino IDE

• PCB Designing using Proteus Professional

• Design Simulation using Proteus Professional

ACHIEVEMENTS:

1. Merit Holder in Higher Secondary School.

2. Developed a Mini Game using Unreal Engine.

HOBBIES:

1. Playing Competitive Video Games.

2. Playing Table Tennis.

DECLARATION:

“I, SAURAV SURI hereby declare that the above furnished information is authentic to the best of my knowledge.”

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