| Distance: | Resume alert | Resumes 1 - 10 of 5849 |
UVM AXI4 Verification Engineer
Ithaca, NY, 14850
... provided by Hebei University of Technology and Florida International University,US) Technical Skills Programming&Scripting:Verilog, SystemVerilog, VHDL, UVM, C/C++, python, Tcl, Perl, Makefile, shell Tools: ModelSim, VS Code, GTKWave, Klayout, ... - Nov 03
... provided by Hebei University of Technology and Florida International University,US) Technical Skills Programming&Scripting:Verilog, SystemVerilog, VHDL, UVM, C/C++, python, Tcl, Perl, Makefile, shell Tools: ModelSim, VS Code, GTKWave, Klayout, ... - Nov 03
Silicon Verification Engineer (UVM/RISC-V)
Virginia Beach, VA
VISHAL JADHAV ********@***.*** +1-602-***-**** http://www.linkedin.com/in/vishal-jadhav-b27ab71a1 OBJECTIVE Aspiring silicon verification engineer with experience in System Verilog based-UVM testbenches, constrained-random and directed testing, and ... - Nov 02
VISHAL JADHAV ********@***.*** +1-602-***-**** http://www.linkedin.com/in/vishal-jadhav-b27ab71a1 OBJECTIVE Aspiring silicon verification engineer with experience in System Verilog based-UVM testbenches, constrained-random and directed testing, and ... - Nov 02
ASIC UVM Verification Engineer
San Jose, CA
... Technical Skills: HDL Languages: Verilog, SystemVerilog Verification Methodologies: Functional Verification, Directed Testing, Constrained-Random Verification, Coverage-Driven Verification Verification Framework: UVM, Testbench Development, ... - Nov 02
... Technical Skills: HDL Languages: Verilog, SystemVerilog Verification Methodologies: Functional Verification, Directed Testing, Constrained-Random Verification, Coverage-Driven Verification Verification Framework: UVM, Testbench Development, ... - Nov 02
RTL & Memory Verification Engineer
New York City, NY
... Hands-on experience with SystemVerilog, Verilog, UVM, Python, RTL simulation, testbench development, constrained-random verification, assertions, functional coverage, and regression testing. Experienced in DRAM, SRAM, DDR4/DDR5 concepts, Processing ... - Nov 02
... Hands-on experience with SystemVerilog, Verilog, UVM, Python, RTL simulation, testbench development, constrained-random verification, assertions, functional coverage, and regression testing. Experienced in DRAM, SRAM, DDR4/DDR5 concepts, Processing ... - Nov 02
Design Verification Manager
Bengaluru, Karnataka, India
... different fields and seek an opportunity for continuous learning TECHNICAL/SOFTWARE SKILLS • Programming Languages: C, Verilog, System Verilog, Perl, ASM • Verification tools: Simvision, Vmanager, Xcelium, Verdi, VCS • Protocols: AXI, AHB, APB, ... - Oct 31
... different fields and seek an opportunity for continuous learning TECHNICAL/SOFTWARE SKILLS • Programming Languages: C, Verilog, System Verilog, Perl, ASM • Verification tools: Simvision, Vmanager, Xcelium, Verdi, VCS • Protocols: AXI, AHB, APB, ... - Oct 31
Senior FPGA DSP Embedded Hardware Engineer
Madrid, Community of Madrid, Spain
... · Role: Schematics and PCB design with OrCad y Mentor Graphics PADS, C/C++ firmware design over ARM Cortex M4 and in Verilog for Lattice FPGA. 4. Sgenia Soluciones, S.A (www.sgenia.com) · Project: Modular Control System for Hydrogen Fuel Cell based ... - Oct 31
... · Role: Schematics and PCB design with OrCad y Mentor Graphics PADS, C/C++ firmware design over ARM Cortex M4 and in Verilog for Lattice FPGA. 4. Sgenia Soluciones, S.A (www.sgenia.com) · Project: Modular Control System for Hydrogen Fuel Cell based ... - Oct 31
Senior Embedded Firmware & Embedded Linux Consultant
Los Angeles, CA
... TCP/Ipv4, TCP/IPv6 Subsystems: Camera, display, audio, flash memory, power management Languages / Tools: C, C++, Python, Ruby, Verilog, VHDL, Xilinx Vivado Test & Debug Instruments: JTAG debuggers, logic analyzers, protocol decoders, oscilloscopes, ... - Oct 28
... TCP/Ipv4, TCP/IPv6 Subsystems: Camera, display, audio, flash memory, power management Languages / Tools: C, C++, Python, Ruby, Verilog, VHDL, Xilinx Vivado Test & Debug Instruments: JTAG debuggers, logic analyzers, protocol decoders, oscilloscopes, ... - Oct 28
FPGA V&V Verification Engineer
Carrollton, TX
... OS : Unix, Linux HDL Languages : Verilog, VHDL HVL Language : System Verilog Simulation Tools : Model-Sim, gcc compiler, gdb debugger, Verilog XL, NcVHDL, VCS, NcVerilog (Cadence- Affirma). Synthesis Tools : DC Shell Linting Tool : Leda (Synopsys) ... - Oct 27
... OS : Unix, Linux HDL Languages : Verilog, VHDL HVL Language : System Verilog Simulation Tools : Model-Sim, gcc compiler, gdb debugger, Verilog XL, NcVHDL, VCS, NcVerilog (Cadence- Affirma). Synthesis Tools : DC Shell Linting Tool : Leda (Synopsys) ... - Oct 27
VLSI Design Engineer (Verilog, FPGA, IC)
Ludhiana, Punjab, India
... Verilog HDL Assembly language of 8085 Microprocessor Assembly language of 8051 Microcontroller Experience: Institute/University Designation Year Place State Guru Nanak Khalsa College Lecturer 2007- 2009 Yamunanagar Haryana IITT College of Engg. ... - Oct 27
... Verilog HDL Assembly language of 8085 Microprocessor Assembly language of 8051 Microcontroller Experience: Institute/University Designation Year Place State Guru Nanak Khalsa College Lecturer 2007- 2009 Yamunanagar Haryana IITT College of Engg. ... - Oct 27
ASIC SoC Design Verification Engineer
Hyderabad, Telangana, India
... Technical Skills: Verification Languages SystemVerilog, Verilog Methodologies UVM, Constrained-Random Verification, Coverage-Driven Verification UVM Components Sequence, Sequencer, Driver, Monitor, Agent, Scoreboard, Environment Assertions SVA, ... - Oct 12
... Technical Skills: Verification Languages SystemVerilog, Verilog Methodologies UVM, Constrained-Random Verification, Coverage-Driven Verification UVM Components Sequence, Sequencer, Driver, Monitor, Agent, Scoreboard, Environment Assertions SVA, ... - Oct 12