Senior ASIC/SoC Verification Engineer - 15+ Years Experience

ANUSHA GANDAVARAPU

Senior ASIC / SoC Design Verification Engineer

Atlanta, GA, USA +1-470-***-**** *****************@*****.*** linkedin.com/in/anusha-gandavarapu-35211927

H-1B Visa Approved March 2026 — Available for Immediate Transfer / Employer Sponsorship

PROFESSIONAL SUMMARY

Results-driven ASIC/SoC Design Verification Engineer with 15+ years of experience delivering first-pass silicon on the world's most complex semiconductor programs — GPU compute shaders and processing units at Arm, PCIe/Ethernet/DMA SoCs at Intel, and DMA subsystems at DisplayLink. Deep expert in System Verilog, UVM, and C-based verification with a proven record of architecting scalable testbenches, closing functional coverage, and identifying critical design bugs before tape-out. Recognized for technical leadership across GPU, networking, DMA, and serial I/O domains at globally distributed teams in the UK, Europe, and India. Actively maintaining technical currency with current AI accelerator verification methodologies and cocotb/Python-based simulation flows.

CORE COMPETENCIES

Verification Languages: SystemVerilog · C · SystemC · DPI

Methodologies: UVM · OVM · VMM · Constrained-Random Verification · Coverage-Driven Verification · Formal Property Checking

Domains Verified: GPU Architecture (Arm Mali) · PCIe · Ethernet · DMA · Serial I/O · Bluetooth · Compute Shaders . AMBA Interconnects (AXI · AHB · APB) – Subsystem & SoC level

Processors / SoC Architectures: ARM Cortex-A9 MPCore · Cortex-A7 · Cortex-M7 · Mali-400 GPU · ARC700 DSP cores · Heterogeneous Multi-Core SoCs .

EDA / Simulation Tools: Synopsys VCS / VCSMX · QuestaSim · Questa Formal · Cadence NCSim · Verdi · Indago · DVT Eclipse

Scripting: Python · Perl · TCL · Makefile

Version Control: Git · ClearCase · SVN

CAREER BREAK — RELOCATION TO USA

International Relocation — UK to USA Jul 2025 – Present

Atlanta, GA, USA

•Voluntarily relocated with family from Cambridge, UK to Atlanta, Georgia, USA after 15+ years of progressive semiconductor career at Arm, Intel, Synaptics, and Ericsson.

•H-1B visa approved March 2026 — available for immediate transfer to a US employer; no lottery risk /waiting period.

•Actively maintaining and expanding technical depth during the gap: advanced UVM and System Verilog coursework, AI accelerator verification methodology study.

•Fully settled, immediately available for full-time employment, and open to remote, hybrid, or on-site roles (willing to relocate within standard timelines) across major US semiconductor hubs.

PROFESSIONAL EXPERIENCE

Senior Verification Engineer · Arm Ltd. · Cambridge, UK Mar 2021 – Jun 2025

•Led block-level functional verification of two of Arm's most complex and performance-critical GPU blocks: the GPU Processing Unit (PU) and Compute Shader Endpoint (CSE), spanning multiple GPU generation releases.

•Architected end-to-end UVM verification environments — drivers, monitors, scoreboards, coverage collectors, and sequence libraries — that became reusable infrastructure across follow-on GPU programs, reducing environment setup effort by ~30%.

•Drove functional coverage closure to 98%+ on PU and CSE blocks through a combination of constrained-random and directed test strategies, directly enabling first-pass silicon tape-out success.

•Developed and executed LLVM-based RIS generation flows, EETB testing, and model debug campaigns that identified and resolved 20+ critical pre-silicon design issues across PU and CSE.

•Partnered daily with GPU architects, RTL designers, and modelling teams to refine verification plans, triage failures, and adapt coverage goals as microarchitecture evolved across design phases.

•Mentored junior verification engineers on UVM coding best practices, constrained-random methodology, and coverage-driven debug — contributing to team capability growth in a fast-paced GPU roadmap environment.

Senior IC Verification Engineer · DisplayLink (Synaptics) · Cambridge, UK Aug 2017 – Dec 2020

•Owned full-cycle functional verification of the DMA Store block in NIVO and VINO multimedia subsystems using System Verilog and UVM, delivering complete coverage closure on a schedule-critical display chip program.

•Validated 10+ complex burst-operation scenarios, alignment-boundary edge cases, and multi-channel data-transfer modes — catching 15+ specification deviations before RTL freeze and preventing costly respin risk.

•Deployed Questa Formal property checking on VINO DMA Store block, augmenting simulation-based coverage and uncovering corner-case bugs that constrained-random simulation could not reach.

•Verified DLMEM blocks using coverage driven verification methodology.

Senior Engineer, Design Verification · Intel Corporation · Bengaluru, India Nov 2014 – May 2017

•Delivered SoC-level verification for 7 subsystems — PCIe, Ethernet, DMA, Serial I/O, GNA, CGU, and SPCU — within a high-complexity Intel platform SoC integrating ARM Cortex-A9, Cortex-A7 and ARC 625 cores, contributing to on-schedule tape-out delivery.

•Designed and implemented a C-DPI co-verification framework bridging legacy C testcases with the System Verilog UVM environment, enabling reuse of 200+ existing test assets and cutting re-implementation effort by ~40%.

•Authored comprehensive SoC-level verification plans and regression suites covering 5,000+ test cases across all subsystems; drove and reported weekly coverage metrics to program leadership.

•Served as primary verification point-of-contact for PCIe and Ethernet subsystems, coordinating with IP vendors, RTL owners, and system architects to resolve 30+ interface-level integration issues.

Senior Engineer · Ericsson · Bengaluru, India Sep 2013 – Nov 2014

•Performed protocol-level PCIe subsystem verification using System Verilog and UVM, covering link training, data-transfer, and error-handling scenarios to full compliance with PCIe Gen2/Gen3 specification within a modem SoC integrating ARM Cortex-M7.

•Led migration of a legacy System-C VRI environment to UVM, modernizing the team's testbench infrastructure and enabling adoption of constrained-random methodology — reducing manual test development effort by an estimated 35%.

•Developed targeted directed and constrained-random testcases for PCIe corner cases; identified and resolved 10+ integration defects during full-chip assembly and regression.

ASIC Verification Engineer · MosChip Semiconductor · Hyderabad, India May 2012 – Aug 2013

•Performed SoC-level verification of Bluetooth subsystem for the wearable/IoT SoC integrating ARM Cortex-A9 MPCore and ARC700 cores, using System Verilog and VMM to achieve full Bluetooth 2.1 + EDR protocol compliance.

•Developed monitors, scoreboards, and constrained testcases for multi-layer protocol validation; maintained regression suites and resolved RTL and verification environment defects throughout the program lifecycle.

ASIC Verification Engineer · Test and Verification Solutions (TVS) · Chennai, India Dec 2011 – Apr 2012

•Verified a TDM protocol-based IP using Specman-e and eRM methodology

•Developed functional testcases and supported regression automation.

Hardware Engineer · Stellar-IP Solutions · Hyderabad, India Jun 2010 – Dec 2011

•Built OVM and System Verilog verification components for GMII and AMBA (APB/AHB) protocol interfaces.

•Supported RTL debug and early hardware bring-up activities on embedded SoC platforms.

EDUCATION

B.Tech — Electronics & Communication Engineering 2005 – 2009

Jawaharlal Nehru Technological University, India

ADDITIONAL INFORMATION

•Experienced working in globally distributed teams across the UK, India, and the US; strong cross-cultural collaboration and remote-team communication skills.

•Deep familiarity with Arm Cortex/GPU IP ecosystem.

•Deep verification experience spanning both IP and SoC/subsystem levels (7+ years each), enabling end-to-end validation from block to full-chip integration.

•Fully remote preferred and immediately available, hybrid, or on-site roles; willing to relocate to Silicon Valley CA, Austin TX, San Diego CA, or Seattle WA.

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