Design Verification Engineer Candidate with Hardware Experience

JEEVITHA DEVALAMPETA

+1-908-***-**** ********.***********@*****.*** LinkedIn: Jeevitha_devalampeta GitHub: RTL-Coding EDUCATION

Bachelor of Technology Electrical and Electronics Engineering Aug 2008 - May 2012 University of JNTU India GPA: 3.5 / 4.0

SKILLS

Programming Languages: Verilog (Certified), System Verilog (Certified), System Verilog Assertions. Scripting Languages: Python, Perl.

Verification Methodology: UVM

Technical Concepts: Digital system Design, RTL Design, Computer Architecture (RISC Pipelining), Functional Coverage, Object Oriented Programming, Debugging, Constrained Randomization Tools: ModelSim, Xilinx ISE design suite, QuestaSim, EDA Playground Protocols: APB, AXI4, AHB, I2C, UART, SPI

PROJECTS

Designed and developed UVM Verification Environment for Synchronous FIFO

● Designed and implemented an 8-bit synchronous FIFO with full/empty flags, overflow/underflow detection, and read/write pointer management using Verilog.

● Implemented Transaction class with packet format, developed directed and random sequences, driver components and Monitor Components (to capture reference and actual packets).

● Conducted random and corner-case testing, focusing on verifying underflow and overflow conditions in the design. Designed and developed UVM Verification Environment for APB Protocol

● Designed APB functionality with finite state machine concept using System Verilog.

● Developed Master, Slave Agents and implemented Test cases.

● Developed scoreboard on my own to maintain effective comparison, Functional Coverage Component. Development of UVM Verification Environment for ALU Design

● Implemented Predictor component to obtain predicted output and to compare it with DUT output.

● Created In-Order Scoreboard, Functional Coverage Component, Sequences, Master and Slave agents. Designed and developed a System Verilog test bench for an AHB-to-APB bridge

Designed and implemented an AMBA AHB to APB Bridge supporting single and burst transfers.

Developed FSM-based control logic handling address/data phases, wait states, and error responses.

Created System Verilog test bench with constrained-random stimulus and functional checks for protocol compliance.

Designed and developed a System Verilog test bench for I2C Protocol

Designed I C slave FSM and verified data transfer using System Verilog master test bench EXPERIENCE

ANOVA, New Providence, NJ May2022 – Present

Performed firmware validation to ensure hardware functionality and defect-free releases.

Configured and tested remote telemetry (RTU) units based on customer specifications.

Ensured reliable wireless communication and device interoperability.

Maintained quality standards by monitoring and verifying RTU unit performance.

Expertise in board-level repair and troubleshooting to identify and address root causes of faults, ensuring effective fixes and providing support to repair teams to ensure efficient resolution of issues. Design and Verification Trainee at ProV Logic (Remote-India) May 2025 - Present

● Gained expertise in Digital Electronics, Verilog, System Verilog, and UVM through hands-on projects with a focus on testbench development, simulation-based validation, and assertion-based techniques.

● Debugged issues such as mismatches between simulation results, resolving corner-case failures during debug and expected timing behavior during project execution. Magna Power Electronics co Inc, NJ Feb 2022 – May2022

Testing, Trouble Shooting and Quality Assurance of Magna Power Programmable DC power supply boards

Performed board level tests on PCBS, Programmable DC power supplies.

Used Schematics, Assembly Drawings, DMM, DVM, Signal Analyzer and Test Fixtures. Repaired Boards and troubleshoot to component level and recorded the failure into the system. IKYA Human Capital Solutions Limited, India Oct 2013-Sep 2017

Managed RFE/ATP surveys, reporting, and RJIL portal submissions.

Conducted site feasibility studies and coordinated installations with cross-functional teams. Bharat Electronics Limited, India Jun 2012 – Sep 2013

Supported electrical design and analysis for defense products.

Assembled, tested, and troubleshot transformers and coils.

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