| Distance: | Resume alert | Resumes 121 - 130 of 5990 |
Abu Dhabi High School
Abu Dhabi, United Arab Emirates
... Hardware: Assembly Language : 8085 Hardware Language : VHDL, Verilog Have good knowledge on PC Hardware EDA Tools: Simulation : ModelSim EE 5.4b, Active-HDL version–3.5, ModelSim, Altera Version 5.4e Synthesis : Exempler Leonardo spectrum version 2 ... - Mar 12
... Hardware: Assembly Language : 8085 Hardware Language : VHDL, Verilog Have good knowledge on PC Hardware EDA Tools: Simulation : ModelSim EE 5.4b, Active-HDL version–3.5, ModelSim, Altera Version 5.4e Synthesis : Exempler Leonardo spectrum version 2 ... - Mar 12
Electrical Engineer Fpga
Tel Aviv, Tel Aviv District, Israel
... Experience on FPGA design in System-Verilog. Proficient in Writing / Defining HW-SW interfaces. Occupational Experience: 2009-2025 Senior FPGA Engineer (ElSpec WizeDsp DSPG Enertec Korentec) Responsibility for all stages of development starting from ... - Mar 11
... Experience on FPGA design in System-Verilog. Proficient in Writing / Defining HW-SW interfaces. Occupational Experience: 2009-2025 Senior FPGA Engineer (ElSpec WizeDsp DSPG Enertec Korentec) Responsibility for all stages of development starting from ... - Mar 11
Electrical Engineer Systems
Bettendorf, IA
Ousmane Lloyd Ntutume ************@*****.*** Phone number: 402-***-**** Address: **** ******* **, *** *, Bettendorf IA, 52722 Objective: Seeking a full-time position as an electrical engineer Skills: •Basic programming (Python, C, java, Verilog, ... - Mar 08
Ousmane Lloyd Ntutume ************@*****.*** Phone number: 402-***-**** Address: **** ******* **, *** *, Bettendorf IA, 52722 Objective: Seeking a full-time position as an electrical engineer Skills: •Basic programming (Python, C, java, Verilog, ... - Mar 08
Digital Design Rtl
Portland, OR
... (Jan 2024 – Mar 2026) Relevant Coursework: Microprocessor System Design, System Verilog, Fund of Pre-Silicon Validation, Computer Architecture, Adv Computer Architecture, Assertion Based Verification, Python & Scripting WKSP. Bachelor of Engineering ... - Mar 06
... (Jan 2024 – Mar 2026) Relevant Coursework: Microprocessor System Design, System Verilog, Fund of Pre-Silicon Validation, Computer Architecture, Adv Computer Architecture, Assertion Based Verification, Python & Scripting WKSP. Bachelor of Engineering ... - Mar 06
Engineering Intern Electronics
Little Elm, TX
... Design System, CST Studio Suite, Ansys HFSS, Xilinx Vivado, Vitis IDE, LT SPICE, Model Sim Programming languages: Verilog HDL, C,Python Operating System: Linux, Windows WORK EXPERIENCE Hardware Engineering Intern, Quantum Computing Inc., New ... - Mar 05
... Design System, CST Studio Suite, Ansys HFSS, Xilinx Vivado, Vitis IDE, LT SPICE, Model Sim Programming languages: Verilog HDL, C,Python Operating System: Linux, Windows WORK EXPERIENCE Hardware Engineering Intern, Quantum Computing Inc., New ... - Mar 05
C++ Full-Stack Web
Sunnyvale, CA
... Proficient in back-end development with C++ and currently learning Verilog and Full-Stack web development. Able to work June 2025 to September 2025. SKILLS Programming Languages: C++ (preferred), Java, Verilog Web Development: Javascript, React, ... - Mar 05
... Proficient in back-end development with C++ and currently learning Verilog and Full-Stack web development. Able to work June 2025 to September 2025. SKILLS Programming Languages: C++ (preferred), Java, Verilog Web Development: Javascript, React, ... - Mar 05
Machine Learning C++
New York City, NY
KEVIN WU 929-***-**** ***********@*****.*** www.linkedin.com/in/kevin-wu-7207b2326 LANGUAGE AND IT SKILLS • Languages: Verilog, Matlab, C/C++, Python, SQL • Other Tools: Cadence Virtuoso, JasperGold, LTspice, Pytorch, CAD, Latex, Linux, MS Office ... - Mar 04
KEVIN WU 929-***-**** ***********@*****.*** www.linkedin.com/in/kevin-wu-7207b2326 LANGUAGE AND IT SKILLS • Languages: Verilog, Matlab, C/C++, Python, SQL • Other Tools: Cadence Virtuoso, JasperGold, LTspice, Pytorch, CAD, Latex, Linux, MS Office ... - Mar 04
Product Manager Data Center
San Jose, CA
... • Applied NLP-based sequence modeling with LSTM architectures to extract and classify malicious signatures in Verilog and VHDL designs, enhancing the accuracy of pattern recognition and threat classification. • Built a cloud-integrated security ... - Mar 03
... • Applied NLP-based sequence modeling with LSTM architectures to extract and classify malicious signatures in Verilog and VHDL designs, enhancing the accuracy of pattern recognition and threat classification. • Built a cloud-integrated security ... - Mar 03
Process Engineer Electrical Engineering
Hillsboro, OR, 97124
... • Designed and executed test scenarios using System Verilog to validate the functionality and timing of the subsystem. Electronics Corporation of India Limited (ECIL) - Hyderabad, INDIA Intern Jan 2021 - May 2021 • Designed an accident detection ... - Feb 26
... • Designed and executed test scenarios using System Verilog to validate the functionality and timing of the subsystem. Electronics Corporation of India Limited (ECIL) - Hyderabad, INDIA Intern Jan 2021 - May 2021 • Designed an accident detection ... - Feb 26
Research Assistant Computer Engineering
Fairfax, VA
... work using cloud functions and RESTful APIs RISC-V ISA Processor Aug 2024 – Dec 2024 • Designed a dual-core CPU in System Verilog using RISC-V ISA with pipelines, caches, and cache-coherency • Verified functionality by creating test-benches, unit ... - Feb 25
... work using cloud functions and RESTful APIs RISC-V ISA Processor Aug 2024 – Dec 2024 • Designed a dual-core CPU in System Verilog using RISC-V ISA with pipelines, caches, and cache-coherency • Verified functionality by creating test-benches, unit ... - Feb 25