Process Engineer Electrical Engineering

Suchitha Reddy Chitta 469-***-**** Hillsboro, Oregon

**************@*****.*** https://www.linkedin.com/in/suchithareddy-chitta Education

University of Texas at Arlington (UTA) - Arlington,Texas Jan 2022 - Dec 2023 Master of Science (MS): Electrical Engineering

Sreyas Institute of Engineering and Technology - Hyderabad, INDIA Aug 2017 - Jul 2021 Bachelor of Technology (Btech): Electronics and Communication Engineering Work Experience

Intel Corporation - Process Engineer Feb 2024 - Nov 2024

• Utilize Hitachi M-9000 series tools and modular plasma etching chambers to enhance productivity in high-volume manufacturing, while standardizing platform and user interface for a smooth transition to 300-mm wafer sizes and ensuring process flexibility for future expansion.

• Collect and analyze data on various parameters to identify trends and implement process improvements, significantly enhancing manufacturing performance across key technology nodes 1274, 1276, 1278, and 1280.

• Sustain manufacturing tools to minimize downtime and enhance operational efficiency, driving improvements in production outcomes across technology nodes.

• Conducted lab testing, DUT validation, and failure analysis on plasma etching chambers to optimize etch profiles, improve tool performance, and enhance process reliability.

Qorvo - Design and Verification Engineer Intern Oct 2023 - Dec 2023

• Designed a system using serial protocols for I2C and SPI integration, creating a configuration register map to conduct reliable read/write operations.

• Integrated peripherals into the existing system, ensuring seamless data synchronization by managing multiple clock domain interactions and mitigating synchronization issues due to internal clock lag using advanced timing solutions like control signal based synchronization, clock stretching and arbitration.

• Designed and executed test scenarios using System Verilog to validate the functionality and timing of the subsystem. Electronics Corporation of India Limited (ECIL) - Hyderabad, INDIA Intern Jan 2021 - May 2021

• Designed an accident detection system, integrating Arduino, GSM, GPS, and sensors, enabling real-time alerts and precise location tracking for enhanced safety.

• Achieved the successful deployment of an advanced accident detection system, improving safety with timely alerts, and accurate location data using cost-effective, energy-efficient components. Technical Skills

• HDL: Verilog, System Verilog, UVM

• Programming Languages: C, Python

• Tools: Cadence Virtuoso, Cadence RTL Compiler, Cadence Innovus, Cadence SimVision, Cisco Packet Tracer, MATLAB/Simulink, Microsoft Office Tools (MS Excel), Linux, JMP, Git, SQL, SPC

• Microprocessors: 8086, 80386DX, EPROM, Flash, SRAM, DRAM, SDRAM, Peripheral Buses (I2C,UART,SPI)

• Electronic Design: CMOS circuit design, Schematic, Simulation, Layout, Debugging and Analysis, Oscilloscope, Multimeter, Combinational and Sequential Circuits

• Clean Room: Wafer Cleaning, Thermal Oxidation, Ellipsometry, Spin-Coating, Diffusion, Doping, Four-Point Probe, Sheet Resistance, Metal Deposition, Photolithography, Etching, Capacitance Measurement, Soft Bake, Metal deposition, Etching, CVD, PVD Relevant Coursework

Semiconductor Device Theory, Analog Integrated Circuit Design, Introduction to MEMS and Devices, Linear Systems Engineering, Digital VLSI Design, Wireless Communication, and IoT, Topics in Digital Systems, Optimal Control, Microprocessor Systems, Silicon IC Fabrication Technology, Silicon IC Fabrication Laboratory (Clean Room). Academic Projects

Dopant Diffusion and Photolithography Study on Silicon Wafer Oct 2023 - Nov 2023

• Engineered n-well formation using P505 spin-on dopant in an N environment, optimizing junction depth by measuring sheet resistance with a four-point probe.

• Optimized photolithography by controlling photoresist coating, UV exposure, and development, improving pattern resolution and fabrication yield

Silicon Wafer Oxidation, Aluminum Deposition, and Etching Study (MOS Cap) Sep 2023 - Nov 2023

• Optimized SiO growth kinetics using the Deal-Grove model, DOE, and SPC techniques, validating oxide thickness via ellipsometry after RCA wafer cleaning.

• Fabricated and characterized MOS capacitors, including 3000Å aluminum deposition, photolithography, wet etching, and C-V analysis using the parallel capacitance-conductance model to assess oxide quality.

.Subway signal and traffic Light Controller using FSMs Jun 2023

• Designed an FSM for subway signal and traffic light controllers with bidirectional I/O pins controlled by tri-state buffers. Optimized designs using state reduction techniques. Implemented using CADENCE VIRTUOSO and Verilog. Advanced CMOS Device Optimization and Chip Area Minimization Jan 2023 - May 2023

• Executed chip physical design with CADENCE INNOVUS to analyze and optimize metal layer configurations to streamline chip area. Ensured a highly compact chip layout in preparation for subsequent enhancements.

• Implemented repeaters using CADENCE VIRTUOSO to achieve significant delay reduction with a lumped interconnect repeater concept. Enhancing signal propagation efficiency in CMOS devices.

• Employed MATLAB for CMOS device optimization to deliver Energy Delay Product (EDP) by 10x through Vdd adjustment. Positioned All-Spin Logic (ASL) and Charged-Coupled Spin Logic (CSL) as CMOS competitors through magnetic delay optimization. SDRAM Controller Design Jan 2023 - Apr 2023

• Designed an FSM for a SDRAM controller to interface SDRAM memory i.e., MT48LC16M4A2 with 80386DX microprocessor having only asynchronous memory support. Created signal for row column and bank selection, data flow, ready logic and refresh support.

• A 132 MHZ clock source was used to clock the SDRAM controller and SDRAM at speed grade -75. Research Paper Presentation on Design and Fabrication of MEMS-based Magnetic Sensors Feb 2022 - May 2022

• The paper discusses the current state and advancements in magnetic field sensor technology, with a focus on MEMS-based devices, and it highlights potential applications and areas for future research in this field.

• Focus on efforts to reduce dampening and electronic noise in MEMS magnetic field sensors and integrating multiple sensors on a single chip. Two-stage Operational Amplifier using CADENCE Virtuoso Nov 2022

• Designed a two-stage CMOS amplifier with the first stage being a Differential Amplifier and the second stage being a Common Source Amplifier and the output buffer with Miller Compensation technique in Cadence Virtuoso Schematic (45nm).

• Met all the specifications such as High Gain of 60dB, Phase Margin of 60 degree, Output swing of 1v, and Power Consumption of less than 0.3mW. Gain Bandwidth of 40MHz, Common mode rejection ratio of 60dB, and Slew rate of 20V/us.

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