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Manager Engineer

Vasant Nagar, Karnataka, India
January 02, 2020

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MOBILE: 897-***-****



1.6+ years of experience in IP/SoC Verification

Currently working on DDR3.

Working experience on Custom ARM SoC Verification

Proficient in UVM, Systemverilog

Good in constrained random verification

Good experience in RTL debugging

Experience in verification architecture plan, test plan, coverage plan, and test case development of various testbench components

Experience in writing Systemverilog assertions / coverage

Experience in coverage driver verification

Good debugging skills

Good Digital and Logic Design knowledge

Knowledge of UVM methodology


Working as DV Engineer from Aug’18 with SION Semiconductors Pvt Ltd, Bangalore

Worked as DV Intern from may’18 to aug’18 with SION Semiconductors Pvt Ltd, Bangalore PROFESSIONAL SKILLS:

HDL Languages Verilog

HVL Languages Systemverilog

Protocol Knowledge AXI-4,AHB,APB

Processor Knowledge ARM Cortex M0

VLSI EDA Tools Aldec Riviera Pro2017.02

Repository Software SVN

Operating Systems Linux, Windows


1.Custom ARM SoC solution for Highend Printer applications –UART Peripherals Client Language used : Systemverilog, Embedded C

Project Description: This SoC is intended to use for Image processing applications such as Printers. It is having ARM CortexM0basedcorewith AHB and APB based bus architecture. Chip support USB,GMAC, Bluetooth, UART, DMA, SRAM, I2C, SPI, ADC, DAC and Timers among other peripherals. Description of Roles: I am part of this SoC verification team and worked on various Embedded C testcases for UART IP verification for ARM integration and functional verification. Currently working on UART IP testcases and bringing up activities from scratch, which is to be integrated onto this SoC. Responsibilities:

Currently working on unit verification of UART IP which is to be integrated to the SoC Working on unit testbench and test cases development of this UART IP from scratch Created test plan to verify UART IPs

Coded C testcases for UART

Debugging of test failures

Found couple of RTL design integration issues.

2.UDP/IPV4 Verification

Language used : UVM, Systemverilog

Project Description: The UDP/IPV4 for 10G Ethernet IP core, integrated UDP,IPV4 and Ethernet(MAC) prococol

.This is a block from HD Video streaming system that transmits video frames over UDP/IP,and the DUT is hardware UDP/IP offload engine that can encode/decode UDP/IP frames. Description of Roles: I am part of this IP verification team and worked on unit-level verification of UDP/IPV4 from scratch .Involved in all phases of the verification.

- Verification architecture, testplans, developing environment, bringing up, testcases writing and delivering milestone phases to the Manager at regular intervals. Responsibilities:

Created full verification environment

Created sequence item, base and master sequence, driver, monitor, agent, scoreboard

environment, base test and top module

Created test config file for test parameters which are used in verification for different testcases

Created test cases for verification like sanity, random, stress, performance, Error testcases.

Found 3+ bugs on this design.


M.Tech in VLSI Design at Banasthali,University, Rajasthan with an CGPA of 72.78% B.Tech in Electronics and communication from RTU,Rajasthan with an CGPA of 68.78% Diploma from UPTU,Lucknow with 72.6%

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