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Electrical Engineering Design

Location:
Jodhpur, Rajasthan, India
Posted:
December 12, 2019

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Resume:

DHARMESH GUPTA

ada15m@r.postjobfree.com 850-***-****

EDUCATION

IIT JODHPUR

BTECH IN ELECTRICAL ENGINEERING

( WITH MINOR IN VLSI ) 2020

CGPA: 7.85* (till 6th sem)

INTERMEDIATE

BHSIEUP 2015

PERCENTAGE: 88.2 %

HIGHSCHOOL

BHSIEUP 2013

PERCENTAGE: 85.33%

COURSEWORK

MAJOR

Analog Electronics

Digital Logic & Design

Digital Signal Processing

Microprocessor & Microcontroller

Microwave Engineering

Communication System

Power System

Power System Protection

Control System

Electrical Machines

Power Electronics

Complex Analysis & Differential Equation

Probability, Statistics & Random Process

Linear Algebra & Calculus

MINOR

Analog & Interfacing circuit*

Digital VLSI Design*

Flexible & Printed Electronics*

(*-ongoing)

SKILLS

PROGRAMMING

C++

WEB TECHNOLOGIES

HTML• CSS

SOFTWARES

Xilinx• Cadence• MATLAB• Simulink•

HFSS

HARDWARE

8085 Microprocessor

INTEREST

Writing • Table Tennis • Liberal Arts

Cricket

PROJECTS

FPGA IMPLEMENTATION OF SENSING SYSTEM *ONGOING

Guide: Dr. Shree Prakash Tiwari ( IIT Jodhpur)

• To design a controller for different kind of environmet sensors like temperature and humidity using FPGA

• To implement the same using verilog module in ISE design suite LINEARIZATION CIRCUIT FOR NTC THERMISTOR USING

OPERATIONAL AMPLIFIERS JAN-APR’19

Guide: Dr. Shree Prakash Tiwari ( IIT Jodhpur)

• Developed a cost effective, linearizing circuit employing non-inverting operational amplifier to linearize exponential ourput of NTC thermistor

• Simulated Using 180nm CMOS technology in Cadence AN INDUCTOR-LOADEDMICROSTRIPDIRECTIONAL

COUPLER FOR DIRECTIVITY ENHANCEMENT JAN-APR’19

Guide: Dr. Soumava Mukherjee ( IIT Jodhpur)

• Used inductor loading to enhance directivity of a 10db directional coupler at 0.9Ghz and drew comparison with conventional counterpart

• Equated even and odd mode velocities to achieve null isolation. DESIGN AND IMPLEMENTATION OF SAMPLING AND

DESAMPLING STAGES AND CALIBRATION OF SURGE

PROTECTION CIRCUIT FOR SENSOR SIGNAL

CONDITIONING SYSTEM AUG-NOV’18

Guide: Dr. Shree Prakash Tiwari ( IIT Jodhpur)

• Designed an ESD protection circuit and verified it for a surge of 2000 V

• Generated control signal for Time Division Multiplexing for sampling and de-sampling stages

• Simulated ESD protection circuit using 180nm technology in cadence design and generated control signal using H-Spice. AERIAL TRAFFIC MONITORING USING GRAPH THEORY

JAN-APR’18

Guide: Dr. Sandeep Yadav (IIT Jodhpur)

• Implemented an algorithm to use surplus available at an airport in emergency crisis or hazardous situation Using graph theory ACHIEVEMENTS AND ACTIVITIES

• JEE advanced2016 Rank: 4100

• Owns a blog at guptadharmesh36.wordpress.com

• Secured 3rd place in Legal Awareness Competition organised by Women Cell, IIT Jodhpur, as part of International Day of Girl Child

• Organised Android Development workshop in annual techno-cultural fest IGNUS’17



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