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Electrical Engineering Design

Folsom, California, United States
August 27, 2018

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Deepa Paul

480-***-**** **** Iron Point Rd, Apt 911, Folsom, CA 95630 Electrical Engineering Graduate, having adept knowledge of VLSI Design/automation (circuit/physical design, synthesis, STA, RTL design and verification), with a focus on digital ASIC design and verification. Seeking full time employment opportunity starting July 2018. Technical Skills and Expertise

• Skills: ASIC Design, Physical Design, RTL Design, RTL Verification, RTL to GDS, STA, CTS, APR, FPGA Design, UVM.

• EDA & Simulation Tools: Cadence (Virtuoso Schematic, Layout Editor, RC Compiler, ICFB, SOC encounter – Floor Planning, Place & Route, Clock Tree Setup), Logic design, Formal Logic equivalence, Logic synthesis, Static timing analysis (STA), Synopsys (DC, ICC2, Hercules, Star RC, Waveviewer, Primetime), HSPICE, Mentor Graphics (Calibre, Model Sim), Genesis2, Gem5 Simulator, Xilinx (ISE, Vivado HLS), MATLAB, Simulink, Tensor flow, Theano.

• HDL & Software languages: Verilog, System Verilog, RTL, C, C++, UNIX Shell scripting, TCL, Perl, Python, MATLAB.

• Coursework: Neuromorphic Computing Hardware design, Constructionist Approach to Microprocessor design, Computer Architecture, Data Structures & Algorithm, FPGA Computing, VLSI Design, Semiconductor Memories, Digital Systems Circuits. Educational Background

• Master of Science in Electrical Engineering GPA: 3.5 Arizona State University, Tempe – AZ August 2016- May 2018

• Bachelor of Technology in Electronics & Telecommunications CGPA: 9.1 Mumbai University, Mumbai, India July 2012-June 2016 Relevant Work Experience:

Teaching Assistant, Prof. Junseok Chae, ASU August 2017 – May 2018

• Tutoring and guiding undergraduate students of Circuits 2 course for Lab Assignments.

• Helped them in troubleshooting circuits and equipment analysis like Signal Generator, Scope, Power Meter, Logic Analyzer Research Assistant, Prof. Hugh Barnaby, ASU April2017 - Aug2017

• Designed event binning circuit for Neutron Gamma Spectrometer (NGS) using Multisim wherein it calculates the number of pulses (gamma & neurons) incoming at the input, developed the board, tested & simulated the NGS at NASA as a prototype. ACADEMIC PROJECTS:

Implementation of Multi Layered Perceptron for a MNIST dataset (7nm FinFET) Jan2018 – April 2018

• Implemented 3-layered neural network with binary weights and activation function as ‘reLu’ using MNIST.

• Trained these weights for optimizing accuracy and implemented it in RTL hardware, synthesized behavioral netlist and performed synthesis by Synopsys DC and APR using cadence Encounter and STA & Power analysis using Synopsys Prime time. (Floor /Power Planning, Clock Tree Synthesis). RISC Processor Aug2017 – Nov2017

• Designed and synthesized single stage version of RISC processor with optimization target of improving performance and IPC.

• Developed modules of Majority3 cell, Sort 6, one hot Priority Encoder, Integrator, Programmable pattern Detector, CSA adder, RISC ALU, piped Sort 6 unit, Finite Impulse Response Filter, First in Last out & Last in First Out system using System Verilog.

• Built test-benches having Instruction cache & Data cache to verify and analyze the functionality coverage and performance. DRAM & SRAM Design June2018 – July 2018

• Designed 6T-SRAM & DRAM cell with Sense-Amplifiers using 32-nm low power PTM model in Hspice. Employed Sub-array techniques to observe Bitline Signal Development time, Bitline Voltage Changes, and Sense-Amp set time. Optimized the design to read in less than 30 ns cycle.

• Performed Static & Dynamic Stability Analysis to calculate READ/ WRITE noise margins. Convolution & Maximum Pooling Engine Design using APR (7nm FinFET) April2017 – May2017

• Implemented a pipelined Convolution & Max-pooling engine with Cadence RTL compiler, synthesized the behavioral Verilog netlist, performed APR (Floor /Power Planning, Clock Tree Synthesis) and timing analysis using Primetime. Design of 16 x 16 Register file with one read and write port (7nm FinFET) March2017 – April2017

• Designed layout for Register file (RF) with 4:16 decoder and 6T- SRAM. Performed post – layout signoff checks like DRC and LVS and timing analysis. Simulated the PEX netlist using HSPICE and aimed for power and area optimizations. Standard Cell Library Design & Design of 8-bit modulo adder (32nm PDK) Jan2017 – Feb2017

• Developed standard cells for XOR, NAND3, DHLx3(9 fins at output node) using Cadence 6 Virtuoso & also designed schematic and layout of 8-bit modulo adder using the D-flipflop and 1-bit adder standard cells. Also performed LVS, DRC checks and analyzed power and performance trends. Minimum EDP is achieved. Cache replacement and Branch prediction techniques implementation (Computer Architecture) Feb2017 – March2017

• Developed a C code to implement cache replacement policies like DIP, SRRIP, DRRIP, etc. on Gem5 Simulator and examined the miss rate and IPC for SPEC benchmark, also static and dynamic branch prediction techniques performance.

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