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Senior Applications Engineer

Location:
San Diego, California, United States
Posted:
August 13, 2018

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Resume:

Manan J. Shah

***** **** ***** ****, **** ****, San Diego, CA 92126 +1-315-***-**** ac6nq4@r.postjobfree.com LinkedIn: https://www.linkedin.com/in/manan-shah-1b804615/ EDUCATION

Syracuse University, Syracuse, New York

M.S., Computer Engineering, May 2012, GPA: 3.4/4.0 Gujarat University, Gujarat, India

Bachelor of Engineering, Electronics and Communication, June 2010, GPA 3.7/4.0 TECHNICAL SKILLS

Hardware Descriptive Languages: VHDL(intermediate), Verilog(proficient), SystemVerilog (proficient) Programming Languages: C, C++, System C (intermediate) Scripting Languages: Tcl, Prel, Python (proficient) Peripherals: USB, UFS, JTAG, PCI-e, SATA

EDA Skills: Simulation (proficient), Emulation (proficient) INDUSTRY EXPERIENCE

Senior Application Engineer, Mentor Graphics a Siemens business, San Diego, CA (August 2017 - Present)

- Took a lead role in deploying the tools low power solutions and also the software debug offerings Application Engineer, Mentor Graphics, San Diego, CA (August 2014 - July 2017)

- Worked on improving the presence of the company's Emulation platform by enabling new and existing users with different features of the Tool

Associate Application Engineer, San Diego, CA (August 2013 - July 2014)

- Shadowed senior AE's to understand the customer environment and to get firsthand experience of the ongoing projects at the customer

Associate Rotation Engineer, Mentor Graphics, Fremont, CA (June 2012 – July 2013)

- Learned and got trained about the company’s emulation tool, Veloce and the various solutions that goes along with the product INDUSTRY PROJECTS

Enabled a software debug solution called “Codelink” which helped the customer replay their software test which is a feature they did not have previously

- Collected the requirement from the customer on CPU for which codelink is required

- Worked with the user in identifying a pilot design in which the feature would be enabled

- Once the project was enabled, conducted several demo’s explaining various features of the solution Enabled a software debug solution “virtual JTAG” which helped the customer to front door load the memories via Trace32 software

- Established a flow working with the local CAD team that would automate the instantiation of relevant module making the feature easy for integration

- Used various techniques to improve the “step-in” (execution) speed of the virtual JTAG solution to bring it at par with physical one

- Created integration documents that allowed any new user to understand the feature and integrate them in their design

- Eventually this resulted into increase in the utilization of Veloce for SW debug and verification Deployed Veloce Power Aware solution which allowed the customer to do emulation based low power verification

- Lead the deployment project from the beginning to the final hand over to the customer

- Conducted numerous training on the Veloce UPF solution communicating to the users on the supported UPF constructs on veloce

- Understood the requirement from the customer on the behavior of the tool and other UPF constructs

- Communicated the requirements back to the product marketing team with appropriate priority

- With this project it allowed the users to run long power aware test case which they could not run in the simulation environment

- The project increased the size of the design and also the utilization of the emulator resources Created a solution “Pass-Thru” jointly with the customer which allowed the sw/fw users to do hw verification

- Designed a solution that allows efficient usage of the emulation products since the user need be tied up to the resource

- Allowed memory flexibility since the memory can be placed either on the TB side or on the client side which is closer to the DUT

- Attained better runtime performance since over UVM based test bench using C/C++ Deployed a Veloce power app feature that enables the customer with Power Estimation and Analysis

- This allowed the users to do RTL power exploration and Gate level power estimation to an accuracy rate of 95%

- Worked with third party vendor to achieve a common goal of creating a flow that generates the power number from “PowerArtist” Summary

- Over 6 years of experience in the Semiconductor industry

- Expertise in functional verifications and solutions offerings

- Skilled in using Linux/Unix environment for projects

- Experienced in understanding customer requirements and providing appropriate solutions

- 5 years of experience in working onsite at the customer location

- Excellent with soft skills and interpersonal communication and believe in team work



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