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Engineer Design

Austin, TX
March 13, 2018

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Tel : 512-***-****

Prasanna K. Ganta


Texas 78759


Electrical Engineer with MSEE / MBA & 20 yrs exp. seeking a position that requires high level innovative Business analysis / Systems analysis / HW / SW Problem solving, Debugging, Standards implementation, Product interoperability issues with Audio, Video, Metadata delivery, hosting & processing over IP networks. Product concepts

Business plans

Product feasibilities

IPTV architecture with LTE Last mile link

TV Guide for Visually impaired

Emergency Alert Service for satellite subscribers

Analog Video Signal Generator

HW/SW Arch



IP Video Head End Architecture;

Audio de-embedder ( FPGA & Host processor interface) Audio Watermarking ( FPGA & Host processor interface) Dolby E ( FPGA & Host processor interface)

SW design Developed SW (C/C++/Matlab) for Real Time Embedded Test & Measurement Video products on barebones 8 /16 bit uControllers, 32 bit uControllers using VxWorks x –compiled with GNU tools on a SunOS/ Solaris platform. HW design Board design ( Schematic entry ORCAD); RoHS redesign. DSP design Moto 56K DSP debug & enhancement

Audience Measurement DSP proofs of concept using MATLAB Audio Watermarking implementation using Analog DSP – Host & FPGA interaction. FPGA design Altera workflow. Audio de-embedder, DSP Watermarking interface; Dolby E board interface; Bit level expertise with AES3 Audio, SMPTE 2022 /259 /274/ 292/ 299, PLL, Clocking; Frame Synchronizer stress tests.

ASIC Coverification Verilog to C; VHDL / RTL to behavioral models; Drivers; Chip Bringup. System Test plans IPTV headend components ( MPEG2/H.264 Decoders, Frame Synchronizers, Switchers etc); Bakeoff tests for SDVN IP switches in the Video headend. Field Support Tier3 and 4 Engineering Field Support. Wrote Manuals, Engineering Change Orders;

Audio Video




Video: SMPTE 259 / 274 /291 / 292 / 299; MPEG2 /H.264 /JPEG, Audio: Dolby AC3/Pulse Audio packets,

Data: AFD, CEA 608/708 Closed Captions, Ad. signaling using SCTE 35/104; IP: SMPTE 2022-<1-6>;

FCC mandates: CVAA Accessibility; CALM Audio, Emergency Alert Systems Advances in ABR

/OTT / Cloud / HDR

Familiar with Cloud based streaming architectures using HLS/Adaptive Bit Rate, Cloud DVR, VoD, HFR, HDR, WCG video formats and Agile & Waterfall development practices. Familiar with AWS Elastic Transcode EC2 S3 Experience

Principal Member of Technical Staff, AT&T Labs, Austin TX 3/2009-5/2017 Lead UVERSE Headend Architect. Plan, Specify, Test & Evaluate SDI uncompressed video, MPEG2 & IP packet based compressed video systems & transport technologies. 1. Developed technical requirements, engineering guidelines, test plans & quantitative engg. analysis for Decoders, Encoders and Video frame synchronizers in the Headend. 2. Subject Matter Expert in SDI Video, Dolby Audio and ASI & IP transcoding. 3. Debugged Cloud / CDN based OTT service using Wireshark to root cause Video freezes. Page 2 of 5

4. Developed VHDL code to program Altera FPGA / Gennum eval boards to create stress test sequences injecting transient synch glitches to evaluate error recovery and resilience od downstream frame synchronizers & encoders. Engaged vendors to fix and test them till they were resolved.

5. Familiar with 4K VoD/HDR, IP SDVN workflows, ABR & HLS OTT video distribution. 6. Experienced with National, Local Ad Insertion ( SCTE 35, SCTE 104) ISILON, SAN, NAS, Omnibus iTX, Thomson Sapphire Playout automation, SinTEC BXF(XML) ad scheduling. 7. Experienced with providing Emergency Alerts for UVERSE using Trilithic EASyCAP. Research & Development

a) Reverse engineered CRC1/CRC2 after modifying Metadata ( Dial Norm) to achieve uniform loudness during program-commercial transitions for Dolby AC3 (SMPTE 337). b) Created a novel method for measuring splicing accuracy for advertisements using SCTE-35 and SCTE-104 splicing protocols to improve splicing accuracy. c) Created a program to decipher the CEA 608 & CEA 708 Closed Caption packet fields in SDI. d) Developed novel method to test SDVN IP 64 port 1 Tbps video switch at full load. e) Created a novel method to vary font color and blur background to enhance readability of user selected CEA708 captions.

f) Created a novel method to deliver GUIDE info for visually impaired subscribers using Client- Server / Cloud for streaming high quality speech from on screen guide saving costs on STB. g) Conceptualized a concert of DVRs in the subscriber network to store and serve VoD & near Live TV in a Peer to Peer configuration saving on data center & CDN costs. h) Conceptualized enhancements to offer EAS on National feeds for Satellite subs. i) Designed failover IP Routing architecture for Barker, Occasional & Short Form channels. Principal Engineer, Nielsen Audio (Arbitron),MD 1/2005 – 2/2009 Design, develop, debug DSP/FPGA/uC based Encoder systems for watermarking audio to enable audience monitoring for TV broadcasters Systems Engineering for SDTV/ HDTV broadcast chains involving complex HW / DSP / FPGA for processing 270 Mbps / 1.485 Gbps uncompressed video stream and AES audio streams.

1. Enhanced product quality by using field support feedback to tighten specifications. 2. Upgraded PCB design using ORCAD for a making an Audio encoder RoHS compliant. 3. Designed HW to interface Dolby E Digital Audio SIMM cards with FPGA; Designed an Analog Video Synch stripper circuit to feed Dolby E Codec card. 4. Debugged / modified FPGA VHDL using Altera Quartus / SignalTap for complex watermarking / SDI Video IP.

5. Extended Host-FPGA interface by adding registers for reading and writing SDI Gennum Deserializer and to condition and draw an asynch error pin into the FPGA. 6. Developed Validation Test plans for video subsystems which reduced audio-video specific field support incidents.

7. Wrote well illustrated User Manual / SDI Quality Whitepaper and facilitated ease of use and integration of Audio Watermarking Encoders in Television Broadcast facilities. 8. Debugged AES Audio Noise due to skipped/repeated samples caused by an unstable Audio Word/Bit clock.

9. Created a novel SDI test signal with multiple jitter spectral peaks to weed out Encoders with poorly performing PLLs (due to poor signal integrity in their control loop) which enabled us to install only the best performing encoders.

10. Developed a novel method to measure PLL frequency response to identify abnormal SDI PLL Page 3 of 5


11. Designed a SDI signal quality assessment process at Broadcast facilities to ensure that Encoders work reliably.

Research & Development

a) Developed an algorithm to synthesize audio word clock field for up-converted SMPTE 292 / 299 streams.

b) Architected & developed VHDL code for a light weight FPGA based Audio Peak / Average Level Meter to repurpose front panel 2 line LCD display to present audio level bars. c) Modeled and simulated using MATLAB, a novel method for matching Audio streams in Audience monitoring application by performing Set Intersections on large data sets using Opto-Electronic interfaces.

d) Developed VHDL code to enable Glitch/Error free switching between two Genlocked SDI streams to create a soft FPGA bypass functionality. e) Reverse Engineered an audio matching scheme by reading source code and modeled it in MATLAB to understand the method’s weaknesses such as poor outcomes in noisy environments, large files & impractical processing times. Staff SW SPE Engineer, Credence Inc, OR 12/2003 - 06/2004 Systems Performance Engineering. Rebuilt Verification, Validation, and Diagnostic application C/C++ software over a modular / shared library based ATE software system architecture for 8 channel / 4 quadrant power supply pin card for 1600 Mbps SoC ATE. Sr.SW Design Engineer, Tektronix, OR 01/2001 – 07/2003 Co verification and SW Design. Built a behavioral model of an ASIC and validate functionality.

• Built a C based shared object library to model Rasterizer ASIC module and co verified with RTL to cut 20% time to develop ASIC drivers.

Chip Bring up and SW Design Developed ASIC drivers to interface with Application SW for High Performance Oscilloscopes.

• Designed chip bring-up drivers for DSP ASIC module. Integrated into Real Time Software Layer for Oscilloscopes.

• Developed DSP debugger, diagnostics. Wrote fixed point VLIW DSP code for trigger positioning calculation.

SW Design Engineer, Tektronix, OR 11/1995 – 01/2001 Cash Award winning Architecture redesign proposal

• Reverse engineered, modeled and re-architected an analog video signal generator to save 300K$ PA.

Video SW Development To develop real time embedded firmware for sustaining instrumentation used to test video signals.

• Experienced with real time embedded C/C++/VxWorks, Motorola 56K DSP, 8X51 Assembler, PLDs and FPGA coding.

• Implemented new Video Test & Measurement features for products and enabled ~20% incremental revenue stream.

• Gained market share by being 1ST to provide HDTV waveform monitoring by modifying x51 code for an older product.

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FPGA Development Application specific Video / Audio design using programmable logic software tools.

• Developed an efficient FPGA scheme to de-embed AES Audio from SDI SDTV/HDTV streams using Altera tools

Software Quality Develop SW Quality plans to assure instrument’s SW functionality.

• Developed PC-DOS RS232 based SCPI test & firmware upload programs. Modified instrument SW for SCPI rear panel instrument interface. Developed software test plans and implemented Million SCPI command stress tests to qualify release. Video Research & Development

• Developed a computationally efficient algorithm for measuring DCT Blockiness in real time based on edge variance.

• Co-evaluated an algorithm for measuring Channel Impulse Response with Tektronix fellow. Gas Turbine Controls Engineer, BHEL Hyderabad, India 7/1992-12/1994 Testing, Erection and Commissioning of Gas Turbine and auxiliary power generation equipment. Education





Electrical Engineering

Computer Science & Engg.


Electronics & Comm. Engg





Oregon Grad Institute, Hillsboro, Oregon

Osmania University, Hyderabad, India

Osmania University, Hyderabad India

Osmania University, Hyderabad India

Skills Skill Level Used How long

SW Broadcast Video & Audio

IP Network Programming & Management

MATLAB, C Programming, JIRA

Unix, VxWorks, Clearcase,Agile Methodology

Tek ASIC VLIW DSP, x51 Assembly, C++









7 years

7 years






HW ORCAD Capture, Quartus Altera FPGA Good 4 years 5y MISC FFMPEG Good Currently 5 y

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• Experienced in SDI Video protocols SMPTE 299 /274/ 259/ 292 at bit level.

• Experienced in analyzing corruptions in Audio AC3/ HE-AAC at a packet level.

• Experienced in Test and Measurement of video (CCIR601/SDTV/HDTV) technologies.

• JPEG Compression with JPEG, Image processing, AES/EBU Audio processing.

• Knowledgeable in Nielsen and Arbitron Audience Monitoring for TV/Radio. Relevant Technology Projects

• Implemented a JPEG Baseline Sequential Image Compression standard for 256X256 monochrome still images using DCT/Huffman encoding with MS-DOS / Turbo C 2.5. Implemented application specific improvements by using a common Huffman table generated from multiple images for faster retrieval and smaller storage space. 1993 Master of Technology (CSE) theses.

• Designed an Audio-Conferencing scheme using UDP Multicast. Implemented a unique simple silence suppressor to reduce network bandwidth during speech silence. 1995 MSEE High Speed Networking.

Awards / Accomplishments

• Awarded Arbitron Award 2008 for fixing issues for European TV broadcasters.

• NAB 1996 Award for Tektronix WFM601M Video Monitor using some of my SW.

• 50% Tuition scholarship from Oregon Graduate Institute for MSEE.

• National Merit Scholarship from Junior College to Bachelor of Engineering.

• 800/800 in Quantitative ability in Graduate Record Exam.

• 11th rank from ~22000 applicants in Entrance Exam for MBA program. Status: US Citizen

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