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Electrical Engineering Design

Tempe, Arizona, United States
February 20, 2018

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**** **** ********** *****, #****, Tempe, AZ 85281 Summary

Electrical Engineering graduate student seeking an Entry level position in Mixed Signal Design/ Verification starting summer 2018. Areas of expertise in Digital/Analog Circuit Design and Layouts. Experience in working with Cadence Virtuoso and Spectre, System Verilog and Matlab.


Arizona state university, Tempe, Arizona Anticipated May2018 Master of Science (MSE) in Electrical Engineering CGPA: 3.87/4 Amrita Vishwa Vidyapeetham university, Coimbatore May 2016 Bachelor of Technology (B. Tech) in Electronics and communication Engineering (ECE) CGPA: 8.2/10 Course taken:

VLSI Design, Constructive approach to Microprocessor design, Hardware acceleration and FPGA,Digital Systems circuits Analog integrated circuits, Semiconductor device theory, Semiconductor memory technologies, Computer architecture. Technical Skills

Design & Simulation tools: Cadence Virtuoso and Spectre, Cadence ICFB, HSPICE,SIMULINK, Modelsim,Prime time, Xilinx ISE, MATLAB, Hercules DRC, Hercules LVS, Star RC Parasitic Extraction,APR,caliber-DRC/LVS Programming languages: Verilog HDL,C,Perl, System Verilog,MIPS,Matlab,Linux. Academic projects

Convolution & max pooling engine in CNN using Verilog module( RTL to GDSII DESIGN) SPRING 2017

● Increased throughput using pipe lined architecture and with fast multipliers and adders for faster computation.

● Performed RTL to GDSII synthesis, Floor planing, power planning and Clock tree synthesis using Cadence Encounter.

● Performed RTL & gate level simulations using Modelsim & post-layout APR timing & power analysis using Synopsis Prime time analysis.

Design a 16-word x 16-bit register file (RF) with 1 write and 1 read port using 7-nm PDK SPRING 201 7

● Designed a full custom 16 entry, 16 bit wide dynamic register file (8T SRAM CELL) using 4x16 Decoder using 3x8 Decoders and Performed DRC, LVS and verified the functionality of the same, obtained the parasitic extraction and performed timing analysis using HSPICE.

Design of 8-bit modulo adder using 32nm Technology with low energy delay product FALL 2016

● Designed using Mirror adder topology and pipe lined architecture to maximize efficiency

● C2MOS Flip flop is used due to its lower layout area and robustness to clock slope

● Performed DRC, LVS checks and Parasitic Extraction using StarRC and HSPICE for functional simulation. Design and verification of MIPS processor and logic blocks using system Verilog SPRING 2017

● Designed and verified several components like Sequential Multiplier, Sequential Divider.

● Designed and verified an R3000 MIPS processor on Genesis2 using System Verilog and Perl, by adding a hazard detection unit and a forwarding unit to avoid data hazards. Design of Standard Cells in 32nm Technology and in 7-nm FinFET Technology FALL 2016

● Developed NOR, NAND and SDFH logic gates with longer transistor widths using Multi-fingering technique

● Performed DRC, LVS checks using Synopsis Hercules, Parasitic Extraction using Star RC and HSPICE for functional simulation. Simulated the extracted PEX netlist from Layout to measure the setup and hold times for Scan D-filflop. Design of cross Point Array memory and STT-RAM FALL 2017

● Implemented the design of Cross Point Array memory with RRAM devices in Hspice and analyzed read and write operations, array size effect on write and read margin,non-linearity effect and sneak path in the RRAM array. Implementation of LRU, LFU and ARC cache replacement policies FALL 2017

● Implemented LRU (Least Recently Used), LFU (Least Frequently Used) and cache replacement policies in C.

● Evaluated the advantages and trade-offs of each of these policies. Design and analysis of fixed point and floating point matrix-vector multiplication hardware using FPGA and ASIC

● Designed a 64x64 matrix-vector multiplication using symphony model compiler with interleaving factors of 4 and 16.

● Mapped these designs to 28nm ASIC designs and on Vertex7 FPGA and performed trade off analysis. WORK EXPERIENCE

Graduate teaching assistant MAY 2017-Present

● Instructing & helping students in performing lab assignments using Cadence for the course EEE 433: Analog integrated Circuit Design and EEE 425: Digital system circuits.

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