| Resume alert | Resumes 31 - 40 of 449 |
Java Engineer
Mountain View, CA
... GPA: 3.66/4.0 - Made Dean’s List in Fall 2018 to Fall 2019, and Spring 2020 Relevant Courses: - Data Structures and Algorithms using Java, Linear Algebra, Formal Language and Computations Technical Skills: - Java, C++, Verilog, some Javascript, some ... - 2021 May 06
... GPA: 3.66/4.0 - Made Dean’s List in Fall 2018 to Fall 2019, and Spring 2020 Relevant Courses: - Data Structures and Algorithms using Java, Linear Algebra, Formal Language and Computations Technical Skills: - Java, C++, Verilog, some Javascript, some ... - 2021 May 06
Verilog, Python, RTL Design
San Jose, CA
... SOC Design using System Verilog, Embedded System On-Chip, Artificial Intelligence using DSP, UVM, Computer Architecture. SGSITS, Indore, MP, India - CGPA - 7.4/10.0 Aug 2014-Apr 2018 Bachelor of Engineering in Electronics & Instrumentation ... - 2021 Mar 17
... SOC Design using System Verilog, Embedded System On-Chip, Artificial Intelligence using DSP, UVM, Computer Architecture. SGSITS, Indore, MP, India - CGPA - 7.4/10.0 Aug 2014-Apr 2018 Bachelor of Engineering in Electronics & Instrumentation ... - 2021 Mar 17
Computer Vision, Deep Learning, Localization, LiDAR processing
Santa Clara, CA
... Skills Development: C++, Java, Python, Tensorflow, Keras, OpenCV, Pytorch, ROS, Gazebo, Javascript, MATLAB, React, Node, MongoDB, Verilog, MIPS Modeling and Analysis: Autodesk Fusion 360, CREO Parametric, Solidworks, Autodesk Inventor, APriori ... - 2021 Jan 25
... Skills Development: C++, Java, Python, Tensorflow, Keras, OpenCV, Pytorch, ROS, Gazebo, Javascript, MATLAB, React, Node, MongoDB, Verilog, MIPS Modeling and Analysis: Autodesk Fusion 360, CREO Parametric, Solidworks, Autodesk Inventor, APriori ... - 2021 Jan 25
Python, Java, SQL, AI, databases, Algorithm, Data Structures
San Jose, CA
... Spring 2020 (Computer Systems & Structure Coursework) Programming Language/Tools Used : Verilog, VCS Simulator • Designed & Verified functionality of Direct Mapped Cache for hits, misses of main memory addresses. Fall 2019 (Human Computer Interface ... - 2021 Jan 24
... Spring 2020 (Computer Systems & Structure Coursework) Programming Language/Tools Used : Verilog, VCS Simulator • Designed & Verified functionality of Direct Mapped Cache for hits, misses of main memory addresses. Fall 2019 (Human Computer Interface ... - 2021 Jan 24
Software Engineering Intern
San Jose, CA
... MongoDB • Operating System: OS X, Enterprise Linux, Ubuntu, Windows • Other technical skills: Android Application development, Verilog, Genism, PySpark, Numpy, TensorFlow, Git, OpenCV, Scikit, Tkinter, PyTesseract, SQLAlchemy, PyMongo PROFESSIONAL ... - 2021 Jan 20
... MongoDB • Operating System: OS X, Enterprise Linux, Ubuntu, Windows • Other technical skills: Android Application development, Verilog, Genism, PySpark, Numpy, TensorFlow, Git, OpenCV, Scikit, Tkinter, PyTesseract, SQLAlchemy, PyMongo PROFESSIONAL ... - 2021 Jan 20
Engineering Engineer
San Jose, CA
... at Omega Inc., 2010-2015 TECHNICAL SKILLS Programming languages: C++, C#, Python, TensorFlow Hardware languages: VHDL, Verilog, SystemVerilog, SystemC EDA tolls: Xilinx Vivado, Intel-Altera designing tools, Cadence Virtuoso Engineering software: ... - 2021 Jan 06
... at Omega Inc., 2010-2015 TECHNICAL SKILLS Programming languages: C++, C#, Python, TensorFlow Hardware languages: VHDL, Verilog, SystemVerilog, SystemC EDA tolls: Xilinx Vivado, Intel-Altera designing tools, Cadence Virtuoso Engineering software: ... - 2021 Jan 06
Electrical Engineering Student
Santa Clara, CA
... statements for components Assembly: Utilizing STM Discovery boards and ARM to program keypad, addressable LEDs, ADC/DAC converters, understanding stacks/recursion/pointers in Assembly FPGA/Verilog: Creating component blocks in Quartus Prime (ex. ... - 2020 Dec 23
... statements for components Assembly: Utilizing STM Discovery boards and ARM to program keypad, addressable LEDs, ADC/DAC converters, understanding stacks/recursion/pointers in Assembly FPGA/Verilog: Creating component blocks in Quartus Prime (ex. ... - 2020 Dec 23
Application Engineer II
Sunnyvale, CA
HARIKA RENDUCHINTALA +1-408-***-**** adivc7@r.postjobfree.com http://www.linkedin.com/in/harikarenduchintala PROFESSIONAL SUMMARY •2+ years of experience coding in Verilog and ASIC/CMOS Design. •Experience building Universal Verification Methodology ... - 2020 Dec 21
HARIKA RENDUCHINTALA +1-408-***-**** adivc7@r.postjobfree.com http://www.linkedin.com/in/harikarenduchintala PROFESSIONAL SUMMARY •2+ years of experience coding in Verilog and ASIC/CMOS Design. •Experience building Universal Verification Methodology ... - 2020 Dec 21
Design Engineering
San Jose, CA
... • Organized and guided activities for students, including assignments and labs for students on combinational and sequential logic theory and circuits, Verilog modeling of Finite State Machines and Advanced computer Architecture. • Assisted and ... - 2020 Dec 10
... • Organized and guided activities for students, including assignments and labs for students on combinational and sequential logic theory and circuits, Verilog modeling of Finite State Machines and Advanced computer Architecture. • Assisted and ... - 2020 Dec 10
RF Support Engineer
San Jose, CA
... California State University, Long Beach GPA: 3.4 Degree conferred: August 2019 SKILLS Languages: Python, C, MATLAB, VHDL/Verilog Tools: Atoll, FDTD, HFSS, CAD, Xilinx, Keil Microvision, Truepath Certifications: CCNA Routing and Switching, Cisco RF ... - 2020 Dec 10
... California State University, Long Beach GPA: 3.4 Degree conferred: August 2019 SKILLS Languages: Python, C, MATLAB, VHDL/Verilog Tools: Atoll, FDTD, HFSS, CAD, Xilinx, Keil Microvision, Truepath Certifications: CCNA Routing and Switching, Cisco RF ... - 2020 Dec 10