Verilog, Python, RTL Design

Parth Sathe

***********.**@*****.*** San Jose, CA 95126 +1-669-***-****

LinkedIn: https://www.linkedin.com/in/parthsathe7/ EDUCATION

San Jose State University, San Jose, CA, USA - GPA: 3.8/4.0 Jan 2020-May 2021 Master of Science in Electrical Engineering

Coursework - Semiconductor Device Physics, Probabilities, Random Variables, and Stochastic Process, ASIC CMOS design. SOC Design using System Verilog, Embedded System On-Chip, Artificial Intelligence using DSP, UVM, Computer Architecture. SGSITS, Indore, MP, India - CGPA - 7.4/10.0 Aug 2014-Apr 2018 Bachelor of Engineering in Electronics & Instrumentation Coursework - Circuit Analysis & Synthesis, Digital Electronics, Sensors & Transducers, Measurement Systems, Analog Electronics, Digital Signal Processing, Filter design and Simulation, Control Systems, VLSI Technology & Design. Achievements

Achieved an All India Rank of 277 and 463, GATE Feb-2019, Feb-2018 TECHNICAL SKILLS

Languages: Verilog, System Verilog, C, Python Scripting, HTML, CSS. EDA Tools: MATLAB, Xilinx ISE Design Suite-Vivado, Synopsys Design Compiler. Design: Analog and Digital IC Design, RTL Coding, Synthesis, Circuit Design Fundamentals, VLSI, Low Power Design. PROJECTS

Error Correcting Code, Hamming Encoder & Decoder (System Verilog, Python, Synopsys VCS), SJSU Oct 2020-Nov 2020

• Improved the flexibility utilizing parameterized data types and recreating system functions to make the design synthesizable.

• Simplified the design by using python to generate an RTL code to make it inexpensive and less complex. Fast Fourier Transform, Decimation in Time (Verilog HDL, Linux), SJSU Jul 2020-Aug 2020

• Upgraded the design from Radix-2 8-point to N-point FFT by constructing an algorithm to compute combinational logic.

• Increased and maintained the speed & accuracy of the output respectively by implanting Half-Precision floating point MACs in the butterfly stages.

SHA-3 256 Permutation Engine (System Verilog, Linux), SJSU Mar 2020-May 2020

• Reduced the timing for complex permutation 3D packed logic to enable the design to run at a given clock time (4.65ns).

• Enhanced the design by adding debug logic (Multiplexers and logic analyzers) in between permutation blocks, used GTK Wave to debug and verify if the values match perfectly after each stage. FIFO with SCAN (Verilog, DFT), EE287, SJSU Feb 2020-Mar 2020

• Designed a FIFO in Verilog HDL, to be placed at the output of a circuit with push, stop, full & empty conditions.

• Added shift registers to the circuit to enable SCAN testing. Synthesized an RTL design to optimize timing, area, and power. (Verilog, Linux), EE287, SJSU Jan 2020-Feb 2020

• Applied quick fixes such as including parentheses in the design, complex gates, conditional operators, changing the position of a signal to fix races and long paths.

• Implemented pipelining to run the design at 200 Mhz. Appended Design Ware libraries to run the design at 300 Mhz. Home Automation Systems, SGSITS Jul 2017-Apr 2018

• Devised the hardware part of the project – utilized temperature sensors, Wi-fi module, IR sensors, Bluetooth module, relays, to make the project versatile. Collaborated with a team of 9 people to target both software and hardware part of the project.

• Eliminated the risk of circuit damage by incorporating 2 IC 555 timers and op amps, which reduces the repetitive switching when the circuit is exposed to unambiguous light intensity. WORK EXPERIENCE

Teaching Assistant, San Jose State University Aug 2020-Dec2020

• Assisted students in conducting lab experiments in principles of communication laboratory (EE160).

• Acquainted students with lab instruments such as oscilloscope, function generator and ADI ADALM2000. Intern, National Institute of Technology Apr 2019-Dec 2019

• Practiced RTL coding, synthesis & simulation in Xilinx Vivado HLx. Compared synthesis results of C and Verilog in Vivado HLs. Intern, Raja Ramanna Centre for Advanced Technology (RRCAT), Laser R&D Department Apr 2017-Jul 2017 • Studied the architecture of STM Nucleo Boards based on ARM Microcontrollers (Embedded C in Keil μ-Vision).

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