| Resume alert | Resumes 21 - 30 of 127 |
Electrical Engineer
Los Angeles, CA
... • Software: C/C++, MATLAB, Python, Machine Learning (TensorFlow), Arduino, x86-Assembly, Verilog PROFESSIONAL EXPERIENCE ARNI UCLA Research Laboratory Los Angeles, CA Research Intern, Information Theory June 2018 – August 2018 Researched Machine ... - 2019 Mar 04
... • Software: C/C++, MATLAB, Python, Machine Learning (TensorFlow), Arduino, x86-Assembly, Verilog PROFESSIONAL EXPERIENCE ARNI UCLA Research Laboratory Los Angeles, CA Research Intern, Information Theory June 2018 – August 2018 Researched Machine ... - 2019 Mar 04
Electrical Engineer Computer Engineering
Los Angeles, CA
... a private server ●Web-based spectral analysis and visualization of vibrational data TECHNICAL / NON-TECHNICAL SKILLS: ●MATLAB, PSpice, CadSoft EAGLE, IAR Embedded Workbench, Verilog, vPython, C Programming Language, LC-3 language, Microsoft Office - 2019 Feb 03
... a private server ●Web-based spectral analysis and visualization of vibrational data TECHNICAL / NON-TECHNICAL SKILLS: ●MATLAB, PSpice, CadSoft EAGLE, IAR Embedded Workbench, Verilog, vPython, C Programming Language, LC-3 language, Microsoft Office - 2019 Feb 03
Design Engineer,Embedded System, VLSI, Verification, Test, C, C++
Los Angeles, CA
... (Tomasulo), Multicore (CMP), VLIW, Superscalar, SMT(HTT), Vector Processors Verification: UVM, Formal Verification, System Verilog Assertion Test Knowledge: DFT, Boundary Scan, ATPG, Fault Simulation Data Transmission Protocols: Cache Coherency ... - 2019 Jan 25
... (Tomasulo), Multicore (CMP), VLIW, Superscalar, SMT(HTT), Vector Processors Verification: UVM, Formal Verification, System Verilog Assertion Test Knowledge: DFT, Boundary Scan, ATPG, Fault Simulation Data Transmission Protocols: Cache Coherency ... - 2019 Jan 25
Computer Engineering System
Los Angeles, CA
... SKILLS: Programming Languages: C++, C, Java Hardware Description Languages: System Verilog, Verilog, System C Scripting Languages: Python, Bash, Perl Verification Methodologies: UVM, FPGA Prototyping, Formal Verification, UPF PROJECTS: Coverage ... - 2019 Jan 23
... SKILLS: Programming Languages: C++, C, Java Hardware Description Languages: System Verilog, Verilog, System C Scripting Languages: Python, Bash, Perl Verification Methodologies: UVM, FPGA Prototyping, Formal Verification, UPF PROJECTS: Coverage ... - 2019 Jan 23
Software Engineer
Los Angeles, CA
... PROGRAMMING SKILLS PROGRAMMING LANGUAGES C/C++ Python MySQL Schell Script Java Ocaml MongoDB PHP Lisp JavaScript HTML/CSS Verilog RELATIVE PLATFORMS & ENVIRONMENTS Docker Nodejs Angular Git Linux OSX PROJECTS Random Number Generator Summer 2018 ... - 2018 Dec 17
... PROGRAMMING SKILLS PROGRAMMING LANGUAGES C/C++ Python MySQL Schell Script Java Ocaml MongoDB PHP Lisp JavaScript HTML/CSS Verilog RELATIVE PLATFORMS & ENVIRONMENTS Docker Nodejs Angular Git Linux OSX PROJECTS Random Number Generator Summer 2018 ... - 2018 Dec 17
Electrical Engineering Design
Los Angeles, CA
... SKILLS Verilog, System Verilog, UVM, C, C++, Python Platforms Cadence Virtuoso, Cadence Innovus, Modelsim, Questasim, Ubuntu, Xilinx Vivado, Visual Studio, Matlabs. PROJECTS Software: Conducted Sort Algorithms, Link list, Graphs(BFS, DFS), Regular ... - 2018 Oct 30
... SKILLS Verilog, System Verilog, UVM, C, C++, Python Platforms Cadence Virtuoso, Cadence Innovus, Modelsim, Questasim, Ubuntu, Xilinx Vivado, Visual Studio, Matlabs. PROJECTS Software: Conducted Sort Algorithms, Link list, Graphs(BFS, DFS), Regular ... - 2018 Oct 30
Student
Los Angeles, CA
... an efficient sorting method • Prepared advertisements for lab equipment on LabX and Ebay platforms SKILLS • Technical: MATLAB, Verilog, R, Python, SolidWorks, Excel, PowerPoint • Communication: Technical Writing, Public Speaking, Debate LEADERSHIP ... - 2018 Sep 27
... an efficient sorting method • Prepared advertisements for lab equipment on LabX and Ebay platforms SKILLS • Technical: MATLAB, Verilog, R, Python, SolidWorks, Excel, PowerPoint • Communication: Technical Writing, Public Speaking, Debate LEADERSHIP ... - 2018 Sep 27
Assistant Engineering
Los Angeles, CA
... Spring 2017 - Design the MIPS in Verilog to be programmed onto an Altera DE0. Awards and Seminars • Presidential Volunteer Service Award (2) August 2014 – May 2015 - Preparation and management in North Campus STEM and environmental club’s events. • ... - 2018 Aug 08
... Spring 2017 - Design the MIPS in Verilog to be programmed onto an Altera DE0. Awards and Seminars • Presidential Volunteer Service Award (2) August 2014 – May 2015 - Preparation and management in North Campus STEM and environmental club’s events. • ... - 2018 Aug 08
Design Electrical Engineering
Los Angeles, CA
... HSPICE Design Synthesis using Synopsys Design Compiler Signal processing and simulation on MATLAB Front-end RTL design using Verilog HDL/VHDL Static Timing Analysis with Synopsys Primetime Place and Route using Cadence Encounter (EDI) Functional ... - 2018 Jul 17
... HSPICE Design Synthesis using Synopsys Design Compiler Signal processing and simulation on MATLAB Front-end RTL design using Verilog HDL/VHDL Static Timing Analysis with Synopsys Primetime Place and Route using Cadence Encounter (EDI) Functional ... - 2018 Jul 17
Electrical Engineering hardware firmware engineer
Los Angeles, CA
... Advanced Driver Assistance System (ADAS) Project using EasySoC-1M Board Sep 2014 - Dec 2014 • Designed FPGA modules through Verilog HDL programming for sensor data processing • Programmed modules of data processing (filtering and mapping) and UART ... - 2018 May 23
... Advanced Driver Assistance System (ADAS) Project using EasySoC-1M Board Sep 2014 - Dec 2014 • Designed FPGA modules through Verilog HDL programming for sensor data processing • Programmed modules of data processing (filtering and mapping) and UART ... - 2018 May 23