| Resume alert | Resumes 11 - 20 of 191 |
Design Engineer Engineering
New Delhi, Delhi, India
... Simulator) Intermediate level MATLAB Intermediate level LTspice Intermediate level PCB design using Proteus Basic level Verilog coding Webench Design Certification From Texas Instruments Job Experience : Currently Working on Company - VVDN ... - 2021 Feb 26
... Simulator) Intermediate level MATLAB Intermediate level LTspice Intermediate level PCB design using Proteus Basic level Verilog coding Webench Design Certification From Texas Instruments Job Experience : Currently Working on Company - VVDN ... - 2021 Feb 26
Student
New Delhi, Delhi, India
... SKILLS • Programming languages: ANSI C, Java, Python • HDL and scripting languages: Verilog and TCL(Basics) • Design and Simulation tools: Xilinx ISE, Cadence Virtuoso, Proteus, MPLab, Matlab, LUMERICAL Device Suite (FDTD, FDE, Charge, Interconnect ... - 2021 Feb 18
... SKILLS • Programming languages: ANSI C, Java, Python • HDL and scripting languages: Verilog and TCL(Basics) • Design and Simulation tools: Xilinx ISE, Cadence Virtuoso, Proteus, MPLab, Matlab, LUMERICAL Device Suite (FDTD, FDE, Charge, Interconnect ... - 2021 Feb 18
Engineer Public School
Delhi, India
... Certification in Verilog & Embedded 5. Certification of Excellence in Participating at CrossRoads- 2018(Spidey The Gas Leakage founder) 6. Certification of Excellence in participating at CrossRoads-2017 (Rain Sensing Wiper) OBJECTIVE Seeking an ... - 2021 Feb 17
... Certification in Verilog & Embedded 5. Certification of Excellence in Participating at CrossRoads- 2018(Spidey The Gas Leakage founder) 6. Certification of Excellence in participating at CrossRoads-2017 (Rain Sensing Wiper) OBJECTIVE Seeking an ... - 2021 Feb 17
Industrial Training Engineer
Noida, Uttar Pradesh, India
... C++ Operating System Linux, Windows Scripting Linux, Python Area of Interest IT Hardware Languages Verilog, System Verilog Others Networking, CCNA TRAINING & PROJECTS Industrial Training Programme In VLSI Design and Verification - DKOP Labs Pvt. ... - 2021 Feb 14
... C++ Operating System Linux, Windows Scripting Linux, Python Area of Interest IT Hardware Languages Verilog, System Verilog Others Networking, CCNA TRAINING & PROJECTS Industrial Training Programme In VLSI Design and Verification - DKOP Labs Pvt. ... - 2021 Feb 14
Design Engineer
Noida, Uttar Pradesh, India
... Trainee) SION Semiconductors Private Limited 07/2020 - Present, Digital Logic Design Concept, RTL Coding using Verilog HDL, Functional Verification using Verilog HDL, Overview of SoC Architectures, Advanced System Verilog Concept, and UVM. ... - 2021 Feb 12
... Trainee) SION Semiconductors Private Limited 07/2020 - Present, Digital Logic Design Concept, RTL Coding using Verilog HDL, Functional Verification using Verilog HDL, Overview of SoC Architectures, Advanced System Verilog Concept, and UVM. ... - 2021 Feb 12
Design Engineering
Noida, Uttar Pradesh, India
... Timing Optimization,Clock Clock wiring,Timing closure, Routing, Timing Analysis Technical Skill Set •HDL languages Verilog HDL •Front end Tools Questa Sim, Xilinx ISE, EDA Playground •Back end Tools Pyxis Schematic,synopsis EDA tools •FPGA ... - 2021 Feb 12
... Timing Optimization,Clock Clock wiring,Timing closure, Routing, Timing Analysis Technical Skill Set •HDL languages Verilog HDL •Front end Tools Questa Sim, Xilinx ISE, EDA Playground •Back end Tools Pyxis Schematic,synopsis EDA tools •FPGA ... - 2021 Feb 12
Engineering Power
New Delhi, Delhi, India
... RTL design trough FPGA Verilog designing Operating Windows C# ASP.Net Mat lab Verilog SQL server I had done my BTECH project on VLSI designing. Title: Multiple Constant Multiplication Algorithm For High Speed And Low Power Designing Environment: ... - 2021 Feb 08
... RTL design trough FPGA Verilog designing Operating Windows C# ASP.Net Mat lab Verilog SQL server I had done my BTECH project on VLSI designing. Title: Multiple Constant Multiplication Algorithm For High Speed And Low Power Designing Environment: ... - 2021 Feb 08
Engineer Design
Noida, Uttar Pradesh, India
... • Knowledge in different modeling languages (VHDL, Verilog-A/AMS, RNM) • Help Cadence customers to setup Liberate Characterization flow for standard cells. • Authored several application notes/ Workshops with the different product engineering teams. ... - 2021 Jan 08
... • Knowledge in different modeling languages (VHDL, Verilog-A/AMS, RNM) • Help Cadence customers to setup Liberate Characterization flow for standard cells. • Authored several application notes/ Workshops with the different product engineering teams. ... - 2021 Jan 08
Medical Electrical
Gurgaon, Haryana, India
... EDUCATION adilw3@r.postjobfree.com 905******* Alwar, India SKILLS (Technical) PSpice & LTspice, Xilinx, Verilog HDL Master of Electronic Science Kurukshetra University (K.U.K). Pursuing B.Sc Electronics Kurukshetra University Kurukshetra (K.U.K) S.A ... - 2020 Dec 12
... EDUCATION adilw3@r.postjobfree.com 905******* Alwar, India SKILLS (Technical) PSpice & LTspice, Xilinx, Verilog HDL Master of Electronic Science Kurukshetra University (K.U.K). Pursuing B.Sc Electronics Kurukshetra University Kurukshetra (K.U.K) S.A ... - 2020 Dec 12
Office Engineering
Delhi, India
... • Languages : C, Verilog • Operating system : Windows Family(XP & 7th edition) • Software & Tools : Xilinx, ModelSim, Tanner Tool, Microwind(Layout), Dev C++, MS Office INDUSTRIALTRAINING: • Organization Course title Duration TATA CMC, Greater Noida ... - 2020 Nov 17
... • Languages : C, Verilog • Operating system : Windows Family(XP & 7th edition) • Software & Tools : Xilinx, ModelSim, Tanner Tool, Microwind(Layout), Dev C++, MS Office INDUSTRIALTRAINING: • Organization Course title Duration TATA CMC, Greater Noida ... - 2020 Nov 17