PREM KUMAR SINHA

E-Mail:-adhw5p@r.postjobfree.com Contact: +91-874*******

CAREER OBJECTIVE:

To secure a challenging position in a reputed organization where I can effectively contribute my skills to achieve success for the organization and myself. ACADEMIC QUALIFICATION:

Examination/Course School/Institute Board/University Year Marks B. TECH

(ECE)

Greater Noida Institute of

Technology, Greater noida

UPTU 2016 79.84%

INTERMEDIATE Techno Model School, Siliguri WBCHSE 2012 79.4% MATRICULATION Tindharia High School, Siliguri WBBSE 2010 65.66% COMPUTER SKILLS AND TOOLS:

• HARDWARE AND NETWORKING from NIIT, Siliguri in 2010.

• Languages : C, Verilog

• Operating system : Windows Family(XP & 7th edition)

• Software & Tools : Xilinx, ModelSim, Tanner Tool, Microwind(Layout), Dev C++, MS Office INDUSTRIALTRAINING:

• Organization

Course title

Duration

TATA CMC, Greater Noida.

VLSI

8th June’15 to 8th July’15

Description: Gained practical knowledge of digital design and chip design.

• Organization

Course Title

Duration

BSNL, Siliguri.

Telecommunication

16th June’14 to 16th july’14

Description: Theoretical knowledge and also visited to exchange office of BSNL and seen multiplexers and other working devices. PROJECT UNDERTAKEN:

• VLSI FINITE

STATE MACHINE

Tools Used: - Xilinx

This project involved the design of a microelectronic system to meet the requirements of a specific application. The system consists of input/output devices coupled with digital logic circuitry, implemented in a single application-specific integrated circuit. The behavior of a system was described using a hardware description language Verilog.

• Low-Power Clock

Distribution

Using a Current-

Pulsed Clocked

Flip-Flop.

Tools Used: - Tanner tool, Microwind (Layout).

This project propose a new paradigm for clock distribution that uses current, rather than voltage, to distribute a global clock signal with reduced power consumption. While current-mode (CM) signalling has been used in one-to-one signals, this is the first usage in a one-to-many clock distribution network. To accomplish this, we create a new high- performance current-mode pulsed flip-flop with enable (CMPFFE) using 45 nm CMOS technology When the CMPFFE is combined with a CM transmitter, the first CM clock distribution network exhibits 62% lower average power compared to traditional voltage mode clocks. ACHIEVEMENTS:

• Awarded trophy in quiz competition in school.

• Awarded medal in football tournament in school.

• Served being HOUSE CAPTAIN in school level.

• Member of Organizing Committee of Techsparks# 14 at GNIOT.

• Qualified Graduate Aptitude test in Engineering (GATE),2017,2018,2019,2020 AREA OF INTEREST/HOBBIES:

• Digital Designing workings and study to higher level parts.

• Software engineering.

• Making friends and communicating with peoples

PERSONAL PARTICULARS:

Name Prem Kumar Sinha

Father’s Name Pramod Kumar Sinha

Date of Birth 23-10-1994

Nationality Indian

Languages Known English, Hindi, Nepali

Address Plot No. 6, Laxmi Singh Road, Patiramjote, Matigara, Siliguri, Dist. - Darjeeling, W.B.

References: Available on request.

Declaration:

I hereby declare that the above mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above mentioned particulars. Date:

Place: (Prem Kumar Sinha)

Contact this candidate