Rajni Dhiman

Nurpur, Himachal Pradesh

855-***-****

adi9uq@r.postjobfree.com

Summary

Application Engineer with 4+ years of experience in Cadence Electronic Design Automation

(EDA) tools: Virtuoso Analog Design Environment, Spectre/ AMS simulators, Liberate standard cell characterization.

Education

C-DAC, Mohali

Master's Degree in VLSI Design

Post-Graduated July 2015

I.E.E.T, Baddi (Himachal Pradesh University)

Bachelor of Technology in Electronics & Comm. Engineering Graduated May 2012

Employment History

Cadence Design System Private Limited

Lead Application Engineer

Noida, Uttar Pradesh

August 2019 – Present

• Responsible for expert level support on Cadence ADE, Spectre EMIR and Reliability methodology. Closely work with internal stake holder to provide accurate, innovative solution to customer.

• Strong exposure in AMS Verification flow of AMS Designer like AMS in ADE, AMS in Hierarchy Editor Flow.

• Knowledge in different modeling languages (VHDL, Verilog-A/AMS, RNM)

• Help Cadence customers to setup Liberate Characterization flow for standard cells.

• Authored several application notes/ Workshops with the different product engineering teams. Cadence Design Systems Private Limited

Sr. Application Engineer

Noida, Uttar Pradesh

October 2016 - July 2019

• Close interaction with Analog/ Analog Mix Signal design engineers for Cadence Analog front end tools, with focus on ADE/ Spectre domain.

• Provide technical support to internal technical publication team to develop the documentation on product flows and their usage.

• Strong expertise in Cadence Analog Design Environment (ADE L/XL/GXL).

• Experience in debugging transistor level Spice circuit simulator issue related to setup or convergence.

• Knowledge of different statistical analysis like Monte Carlo/ Corner, Optimization. Cadence Design Systems Private Limited

Internship

Noida, Uttar Pradesh

August 2015 – September 2016

Achievements

• Achieved Operational Excellence award (four times) in Cadence Design Systems for maintaining good survey score, turnaround-time and overall customer satisfaction.

• ‘Master Level Author’ title attained for publishing the good number of articles and Application Notes on product flows.

• IEEE transaction on "Memristor based ternary content addressable memory (MTCAM) Cell", published in: 2015 2nd International Conference on Recent Advances in Engineering & Computational Sciences (RAECS).

• Qualified GATE in 2013 & 2015.

• Qualified UGC-NET in 2015.

Languages

Hindi and English

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