| Distance: | Job alert | Jobs 131 - 140 of 3203 |
Staff RTL Engineer, Ingress/Egress
Eridu AI
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Saratoga, CA, 95071
... Solid understanding of FPGA or ASIC design methodologies, including synthesis, simulation, and verification tools (e.g., Verilog, VHDL, Synopsys, Cadence). Experience with Ethernet networking protocols (e.g., IEEE 802.1Q, 802.1p, 802.1ad). Knowledge ... - Oct 24
PMU Design Verification Engineer: Analog & Mixed Signal Engineer
Apple
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Austin, TX, 78703
... + Proficient in hardware descriptive languages: Verilog, System-Verilog, and/or Verilog-AMS code. + Familiarity with authoring analog assertion checks to catch bugs. + Capability to identify failure mechanisms and review verification results in ... - Oct 27
FVCTO - Formal Verification Architect
Intel Corp.
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Austin, TX, 78719
... Engineering, Computer Engineering, Computer Science or a related field with 4 years relevant experience or schoolwork Experience in the following: * RTL languages like System Verilog or VHDL Assertion languages like SVA, formal verification. ... - Oct 20
ASIC Design Verification Engineer
AvicenaTech
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Sunnyvale, CA, 94087
... Experience with hardware description languages (HDL) like Verilog/SystemVerilog for basic design understanding. Exposure to physical layer (PHY) or mixed-signal verification concepts. - Nov 10
Campus FPGA Engineer (Intern)
Jump Trading
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Chicago, IL, 60602
... or related areas * Experience with FPGA or other hardware/systems design and development * Experience with RTL (SystemVerilog/Verilog/VHDL) * Previous internship experience in hardware or low-level software engineering * Experience with C, C++, or ... - Nov 06
Senior Digital Verification Engineer
Ethan Alexander Group
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San Francisco, CA
180000USD - 210000USD per year
... Strong knowledge of Verilog or VHDL, C. Capable of scripting and leveraging automation. Able to set up and maintain automated regressions. Ability to understand design specifications and map them to a test plan. Ability to implement test plans. ... - Nov 15
Sr. DFT Engineer
Ambarella
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Manhattan, NY, 10017
... * Knowledge of DFT fundamentals * Knowledge of Logic design and timing * Knowledge of Verilog and Python * Knowledge of Mentor Tessent tools is a plus * Knowledge of scan diagnostics is a plus The base salary range is $135,000 - $196,000. ... - Oct 21
Physical Design Engineer
Apple Inc.
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Cupertino, CA, 95014
... Physical construction, Integration and Physical Verification Shown Knowledge of Basic SoC Architecture and HDL languages like Verilog to be able with logic design team for timing fixes Power user of industry standard Physical Design u0026 Synthesis ... - Oct 22
Principal DFT Design Verification Engineer
Ampere Computing LLC
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Santa Clara, CA, 95053
... You will write test benches using System Verilog and UVM. DFT DV work at Ampere is interesting, challenging, and will expand pre-silicon verification to silicon debug. We like to bring out the best in people, teach each other, and produce products ... - Oct 23
SoC DFT Engineer
Apple Inc.
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Austin, TX, 78719
... Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools. Knowledge of industry standards for DFT and design tools. Proven Understanding of design verification (DV) methodologies for validating DFT implementation ... - Oct 26