| Distance: | Job alert | Jobs 161 - 170 of 1101 |
Senior Silicon Validation & Prototyping Engineer
Experis
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Morrisville, NC, 27560
... Develop Verilog RTL and assist in building Synopsys HAPS prototyping platforms. Perform electrical and logic validation of DDR/HBM subsystems. Develop C/C++ test platforms and Python scripts for test vector generation. Collaborate closely with ... - Jul 14
Electrical Engineer - Sr. Member Engineering Staff
L3Harris Technologies
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Camden, NJ, 08103
... Familiarity with hardware description languages like VHDL or Verilog is a plus. Familiarity with standard electronic interfaces, such as: I2C, USB, RS-232, Ethernet, SATA, PCIe U.S. Citizenship required. Must have and maintain a U.S. Government ... - Jul 28
DFD (Design for Debug) RTL Execution Lead
Microsoft Corporation
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Union Hill-Novelty Hill, WA, 98053
... * Highly Proficiency in System Verilog & scripting along with excellent knowledge of front-end tools (Verilog simulators, Connectivity tools, CDC checkers, low power static checkers, linting). * Understanding in clock crossing techniques & UPF (Low ... - Jul 20
Senior Verification Engineer, CPU Performance
NVIDIA
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Banaswadi, Karnataka, 560033, India
... Hands-on experience with HDLs such as Verilog / System Verilog. Knowledge of verification methodologies and tools for IP and SoC level verification. Experience with System Verilog, C/C++, Python languages and relevant frameworks. Background with ... - Jul 20
ASIC Engineer, Design Verification
META
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Honolulu, HI, 96814
... in the job offered or in an engineering-related occupation Requires three years of experience in the following: System Verilog / UVM Constraint Random Testbench IP/SoC (System On Chip) Verification Debugging design Functional Coverage Automation ... - Jul 28
Senior Staff ASIC Design Engineer, Neural Processor
Syntiant
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Redwood City, CA
$165,000 - $185,000
... RTL implementation of Digital Signal Processing algorithms, using Verilog or System Verilog. Implementation of test benches and digital verification methods. Experience in PPA (Power/Performance/Area) optimizations. Programming/scripting languages ... - Jul 12
RTL Engineer- CPU Load/Store Unit (LSU)
Tenstorrent
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Austin, TX, 78719
... Responsibilities: RTL design and Microarchitecture of the Load/Store unit for a from-scratch high performance CPU based on RISC-V ISA, working closely with the DV and PD team RTL coding in Verilog leveraging on both industry tools as well as open ... - Jul 07
ASIC Design Engineer
Jobot
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Atlanta, GA
... Develop RTL designs using hardware description languages (HDL) such as Verilog and SystemVerilog. 2. Utilize scripting languages like TCL and Python to automate and optimize design flows. 3. Perform synthesis, place and route, and timing closure ... - Jul 26
Senior ASIC Design Engineer
Fermilab
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Batavia, IL, 60510
... Models circuit networks and system components in hardware-description languages (Verilog-A and Verilog/SystemVerilog). Building test benches and carries out analog and/or RF circuit simulations. Executing physical and functional circuit and system ... - Jul 21
Silicon Engineer, Design Verification, Quantum AI
Google
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Mountain View, CA
$156,000-$229,000 +
... Develop and maintain constrained-random verification environments using System Verilog and UVM. Create and execute verification plans and test cases. Identify and debug verification failures. Close coverage measures to identify verification holes ... - Jul 27