| Distance: | Job alert | Jobs 151 - 160 of 3253 |
Mixed-Signal Behavioral Modeling Engineer
Apple Inc.
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San Diego, CA, 92140
... You will write scripts and simple tools for automating repetitive tasks or performing calculations.Excellent knowledge of digital logic gates, clocking and state elements Excellent knowledge of Verilog/SystemVerilog with ability to write behavioral ... - Nov 01
ASIC Design Verification Engineer
AvicenaTech
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Sunnyvale, CA, 94087
... Experience with hardware description languages (HDL) like Verilog/SystemVerilog for basic design understanding. Exposure to physical layer (PHY) or mixed-signal verification concepts. - Oct 22
SR ASIC Verification Engineer
Advanced Micro Devices, Inc.
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Santa Clara, CA, 95051
... KEY RESPONSIBILITIES: * Familiarity with UVM, System Verilog, and C or C++ * Basic experience with System Verilog simulators and waveform debuggers * Exposure to developing and executing test plans for Unit/IP/Subsystem/SOC level verification * ... - Oct 25
Emulation Verification Engineer
Apple
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Beaverton, OR, 97075
... that aids with emulation activities, using Verilog/System Verilog/UVM - Develop random stimulus infrastructure by reusing existing UVM simulation constraints **Minimum Qualifications** + Minimum of BS + 3 years relevant industry experience. ... - Oct 19
Future Opportunities- Software Engineering
Epirus
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Torrance, CA, 90504
... 2+ years of experience in development in C and C++ Bachelor's in Computer Science, Electrical Engineering, Computer Engineering, or related field, Experience with one or more modern systems language(s): Python, Java, VHDL, Verilog, Go, Rust, etc. ... - Nov 11
FPGA Design Engineer
Sperry Rail Service
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Shelton, CT, 06484
... Knowledge of Verilog, SystemVerilog, or High-Level Synthesis (HLS). Familiarity with high-speed communication interfaces (PCIe, Ethernet, DDR, JESD204). Exposure to embedded processors and FPGA SoCs (Nios II, MicroBlaze, ARM cores). Experience with ... - Nov 10
SOC Verification Engineer
Apple
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Waltham, MA, 02454
... + Expertise in HVL and HDL (System Verilog, Verilog). + Advanced knowledge of HVL methodology (UVM/OVM/VMM). + Solid verification skills in problem solving, constrained random testing, and debugging. + Solid understanding of reusable verification ... - Nov 16
SOC Verification Engineer
Apple
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San Francisco, CA, 94103
... + Expertise in HVL and HDL (System Verilog, Verilog). + Advanced knowledge of HVL methodology (UVM/OVM/VMM). + Solid verification skills in problem solving, constrained random testing, and debugging. + Solid understanding of reusable verification ... - Nov 16
SoC DFT Engineer
Apple Inc.
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Austin, TX, 78719
... Knowledge of Verilog and/or VHDL, and experience with simulators and waveform debugging tools. Knowledge of industry standards for DFT and design tools. Proven Understanding of design verification (DV) methodologies for validating DFT implementation ... - Oct 19
SOC Verification Engineer
Apple
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San Diego, CA, 92108
... + Experience in HVL and HDL (System Verilog, Verilog). + Knowledge of HVL methodology (UVM/OVM/VMM). + Solid verification skills in problem solving, constrained random testing, and debugging. + Solid understanding of reusable verification framework. ... - Nov 16