| Distance: | Job alert | Jobs 151 - 160 of 1144 |
Senior ASIC Design Engineer
Fermilab
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Batavia, IL, 60510
... Models circuit networks and system components in hardware-description languages (Verilog-A and Verilog/SystemVerilog). Building test benches and carries out analog and/or RF circuit simulations. Executing physical and functional circuit and system ... - Jul 21
Silicon Engineer, Design Verification, Quantum AI
Google
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Mountain View, CA
$156,000-$229,000 +
... Develop and maintain constrained-random verification environments using System Verilog and UVM. Create and execute verification plans and test cases. Identify and debug verification failures. Close coverage measures to identify verification holes ... - Jul 27
ASIC Engineer, Design
Meta
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Sunnyvale, CA
... Degree must be completed prior to joining Meta 2+ years of experience in micro-architecture and RTL development for complex control and data path IPs OR Experience in SoC Micro-architecture, Design and Integration RTL development using Verilog, ... - Jul 29
ASIC Engineer, Design
Meta
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Sunnyvale, CA
... Responsibilities: ASIC Engineer, Design Responsibilities: Architecture exploration Micro-architecture development RTL development using Verilog, System Verilog and HLS Soft and hard IP identification, selection and integration Collaboration with ... - Jul 29
Embedded Software Architect-Technical Staff
MIT Lincoln Lab
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Lexington, MA
... Working knowledge of circuit simulation tools such as PSpice Experience with FPGA firmware development using VHDL, Verilog or System Verilog to model, design, simulate, test and implement FPGA-based systems Experience in designing electronics ... - Jul 31
Senior Software Engineer, Hardware Tools and Methodology Development
NVIDIA
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Santa Clara, CA
... cross functional teams Improve algorithms (in C++) for automated connectivity, auto logic insertion and post processing Verilog RTL Improve quality of existing tools and flows used by the team What we need to see: BS or MS (preferred) degree or ... - Jul 10
RTL Design Engineer
IBA Infotech
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Santa Clara, CA
... Job Description Role: (RTL) Design Engineer Location: Santa Clara, CA (Hybrid negotiable) Interview: Phone/Skype We're looking for a seasoned RTL engineer with 7+ years of experience in #RTLDesign #Verilog #VLSI #CDC #STA #Synthesis #DFT #Python ... - Jul 26
RTL Engineer- CPU Load/Store Unit (LSU)
Tenstorrent
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Rollingwood, TX, 78716
... Responsibilities: RTL design and Microarchitecture of the Load/Store unit for a from-scratch high performance CPU based on RISC-V ISA, working closely with the DV and PD team RTL coding in Verilog leveraging on both industry tools as well as open ... - Jul 07
RTL Engineer- CPU Load/Store Unit (LSU)
Tenstorrent
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Austin, TX, 78719
... Responsibilities: RTL design and Microarchitecture of the Load/Store unit for a from-scratch high performance CPU based on RISC-V ISA, working closely with the DV and PD team RTL coding in Verilog leveraging on both industry tools as well as open ... - Jul 07
Research Engineer
Galois
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Portland, OR
... Knowledge of hardware engineering languages and platforms such as VHDL, Chisel, Bluespec, SystemVerilog, and Verilog.Security and Citizenship Requirement The employee must be able to obtain and retain a DoD Secret security clearance. The employee ... - Aug 02