| Distance: | Job alert | Jobs 151 - 160 of 1088 |
ASIC Engineer, Design Verification
META
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Topeka, KS
... in the job offered or in an engineering-related occupation Requires three years of experience in the following: System Verilog / UVM Constraint Random Testbench IP/SoC (System On Chip) Verification Debugging design Functional Coverage Automation ... - Jul 16
ASIC Engineer, Design Verification
META
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Cheyenne, WY, 82007
... in the job offered or in an engineering-related occupation Requires three years of experience in the following: System Verilog / UVM Constraint Random Testbench IP/SoC (System On Chip) Verification Debugging design Functional Coverage Automation ... - Jul 16
Senior Hardware Engineer
Microsoft Corporation
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Redmond, WA, 98052
... Responsibilities • Design, propose and oversee the analysis/evaluation of hardware architectures • Design and code RTL modules written in Verilog / SystemVerilog and targeting FPGAs • Simulate and perform hardware-based testing, debug, and ... - Jul 24
Senior Mixed-Signal Design Verification Engineer
Capgemini Engineering
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Santa Clara, CA, 95053
... Deep expertise in SystemVerilog, UVM, and SV Assertions, with a strong foundation in Verilog-HDL and scripting. Proven success in verifying ARM Cortex-based SoCs and working with interfaces such as GPIO, UART, SPI, SW, JTAG, and I2C. Proficient with ... - Jul 26
Senior Verification Engineer
Microsoft
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United States
$ $158,400 - $258,000 per year
... • Build scalable constrained random verification environment in system Verilog using prevalent verification methodologies. • Create comprehensive test plans to address functional scenarios in discussions with the software and hardware design teams. ... - Jul 25
Staff FPGA Engineer - Rolling Meadows, IL
Epiq Design Solutions
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Rolling Meadows, IL, 60008
125000.0-150000.0 per year
... systems Excellent problem-solving and analytical skills Proficiency in hardware description languages (HDLs), such as VHDL or Verilog Deep understanding of the FPGA implementation process including synthesis, place and route, and timing closure ... - Jul 23
Security Engineer, Silicon
Google
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Sunnyvale, CA
$141,000-$202,000 +
... 2 years of experience in Verilog/SystemVerilog. Preferred qualifications: 5 years of experience in software development and security engineering. Experience with Hardware, Firmware, Systems Programming. Experience with Hardware System Architecture. ... - Jul 18
GPU Logic Design Engineer
Intel
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Phoenix, AZ, 85003
... implementation challenges with a focus on schedule + Strong verbal and written communication skills Good understanding of verilog and system verilog, synthesizable RTL + Knowledgeable in modern design techniques and energy-efficient/low power logic ... - Jul 10
Senior Analog Design Engineer
Cypress HCM
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Suwanee, GA
... experience in analog design Experience with low power design using advanced deep micron process Experience with Verilog RTL coding, including synchronous and asynchronous machines Experience with PrimeSim HSPICE and other analog simulators ... - Jul 26
System-on-Chip Design Engineer
Millennium Software and Staffing
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Hayward, CA, 94557
... of experience on SOC, SystemVerilog/UVM methodology Basic Python Scripting experience is required TOP SKILLS: SOC UVM, System Verilog Integrate GPU, CPU, Arm Based System PCIe, DDR, Ethernet, Bus Protocols Python Scripting – Candidate should have ... - Jul 18