Design Electrical Engineer
Resume:
SRIRAMSHARM KALLURI
Email: *********@********.***
Address: **** * ***** ** *** 126
City: TEMPE
State: AZ
Zip: 85281
Country: USA
Phone: 209-***-****
Skill Level: Entry
Salary Range: $70,000
Willing to Relocate
Primary Skills/Experience:
Verilog, System Verilog, VHDL C, C++, Java, Perl, Tcl/Tk, JMP, Design Expert Matlab, Silvaco Atlas, Microsoft office suite, Linux, win 98/ME/2000/XP, Mac OS X Design Compiler (Synopsys), SoC Encounter, Cadene Virtuoso, Synopsys Custom Designer, Xilinx ISE Simulator, Synplify Premier
Educational Background:
Masters Degree, ELECTRICAL/ELECTRONICS ENGINEERING
ARIZONA STATE UNIVERSITY, 08/2010 - 05/2012
TEMPE, AZ
Bachelors Degree, ELECTRONICS AND COMMUNICATIONS ENGINEERING
JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY, 10/2004 - 05/2008
HYDERABAD, AP, India
Job History / Details:
SRIRAM SHARMA KALLURI
1011 E. Lemon St. Apt# 126 * Tempe, AZ 85281 * 209-***-**** * *********@*****.***
ELECTRICAL ENGINEER
Highly skilled with a Masters in Electrical Engineering with specialization in Solid State Electronics, Device Physics, and VLSI engineering, comprised of a solid record of comprehensive and progressive training and project experience, with expertise in: Solar Cells Fabrication, Layout verifications, Digital design, Simulation, Functional verification, Architectures, Design for Test, MATLAB programming, Scripting, and Wireless communication and digital signal processing. Mastery of all phases of project life cycle, with highly developed and effective analytical, diagnostic, innovative and proactive approaches to identifying and solving complex problems. Brings outstanding resolve to the achievement of all tasked goals and objectives.
CORE COMPETENCIES
* The entire fabrication process and characterization of Monocrystalline Solar cells and Heterojunction Solar Cells.
* Experience in layout verifications, including: DRC, LVS, and ERC checks.
* Experience in ASIC flow and Digital design, including: RTL coding, Simulation, Functional verification and Synthesis.
* Familiarity with software design, control systems and manufacturing processes.
* Strong knowledge of Verilog with logic design skills.
* Solid knowledge on on-chip bus architectures, standard bus architectures, I/O protocols and memory controller design.
* Solid working knowledge of AMBA protocol.
* Strong working knowledge of Design for Test, DFT principles, BIST/MBIST, and SCAN.
* Solid understanding of embedded microprocessors and computer system architecture.
* Good MATLAB programming and familiar with Simulink and Labview.
* Expertise at PERL/TCL/Shell scripting skills and C/C++ /Java programming skills.
* Strong academic experience on several Design tools and ASIC/FPGA Synthesis tools.
* Good understanding of wireless communication and digital signal processing like FFT, FIR, etc.
EDUCATION
MASTER OF SCIENCE (M.S.), ELECTRICAL ENGINEERING (SOLID STATE ELECTRONICS); 2012
Arizona State University - Tempe, AZ; GPA: 3.32
* RELEVANT COURSE WORK: Fundamentals of CMOS Fabrication & MEMS; Fundamentals of Solid State Devices; Semiconductor Process/Device Simulation; Analog IC Design; Semiconductor Characterization; VLSI Design; Design of Experiment; Semiconductor Device Theory; Nanofabrication/Characterization; Advanced MOS Devices; and Advanced Hardware System Design.
* MEMBER, ASU IEEE student chapter 2010 - 2012
MASTER OF SCIENCE (M.S.), ELECTRICAL ENGINEERING (VLSI ENGINEERING); 2010
Jawaharlal Nehru Technological University - India
* RELEVANT COURSE WORK: Advanced Digital Design; Design/Simulation/Verification Methodologies using Verilog; VLSI ASIC Synthesis & Design for Testability (DFT); VLSI Physical Design & SoC`s, VLSI Architecture for RISC Processors & DSPs; and Programming & Scripting Languages.
BACHELOR OF SCIENCE (B.S.), TECHNOLOGY IN ELECTRONICS & COMMUNICATION ENGINEERING; 2008
Jawaharlal Nehru Technological University - India
* RELEVANT COURSE WORK: Signals and Systems; Digital Communications; Digital Signal Processing; Digital Image Processing; Digital IC Applications; Analog IC Applications; and Computer Architecture.
* EXECUTIVE MEMBER, VBIT IEEE student chapter 2006 - 2008
* SPORTS CAPTAIN, VBIT 2005 - 2006
* TEAM MEMBER, JNTU Regional Cricket Team
EXPERIENCE
SOLAR POWER LABORATORY, ASU RESEARCH PARK - Chandler, AZ
VOLUNTARY RESEARCH AID, 2012 - Present
Charged with performing experiments, using Design of Experiments approaches for determining the ideal conditions in order to achieve uniform pyramidal texturing across the Monocrystalline Heterojunciton Solar Cell and minimizing the formation of -Crystallites- between the pyramids, resulting in the increase of surface passivation and decrease surface recombination velocity leading to better solar cell efficiency. Accountable for determining the ideal process for obtaining uniform pyramidal texturing on HJT solar cells, and developing a methodology for enabling a repeatable process of texturing. Assist in fabricating standard solar cells as required.
SOCTRONICS PVT. LTD. - Hyderabad, India
STUDENT INTERN, 2009 - 2009
Collaborated with the Physical Design Team in performing layout verifications, including DRC, LVS and ERC checks. Designed and developed I2C bus in Verilog and built test bench and test cases to verify its functionality.
PROJECTS
Design of 8-BIT Fir Filter, COURSE: VLSI Design
* PROJECT: Design an 8-bit energy efficient FIR filter with 0.25m CMOS technology. TOOLS: Cadence custom IC design tools (Virtuoso schematic entry tool, Virtuoso Analog Simulation tool with Spectre Simulator, Virtuoso layout editor).
FD-SOI versus bulk MOSFETs, COURSE: Advanced MOS devices
* PROJECT: To simulate and compare the short channel effects in bulk MOSFETs and Fully Depleted Silicon-On-Insulator. TOOL: Silvaco Atlas.
Traffic light controller, COURSE: Design and verification methodologies using verilog.
* PROJECT: Design and verification of a finite state machine traffic light controller module using verilog. SIMULATOR: NC verilog.
Analysis of performance of a Power MOSFET, COURSE: Design of Experiment
* PROJECT: To determine the efficiency of the Power MOSFET, at different bias conditions and select the condition that gives the best performance. TOOL: JMP.
Multi-cycle Implementation of MIPS processor
* PROJECT: Design and implementation of multi-cycle MIPS processor for a given subset of instructions. HDL: VHDL
Implementation of 3D Mazes
* PROJECT: Develop an algorithm to discover whether or not a path exists through a 3D maze from a starting cell to an ending cell. TECHNOLOGIES: C++, Linux.
TECHNICAL PROFICIENCIES
Programming skills: C, C++, Java, Perl, Tcl/Tk
Hardware Description Languages: Verilog, System Verilog, VHDL
ASIC Synthesis Tools: Design Compiler (Synopsys)
Physical Design Tools: SoC Encounter, Cadene Virtuoso, Synopsys
Custom Designer.
FPGA Synthesis Tools: Xilinx ISE Simulator, Synplify Premier
Software Packages/Tools: Matlab, Silvaco Atlas, Microsoft office suite
Data Analysis/Statistical Tools: JMP, Design Expert
Operating systems: Linux, win 98/ME/2000/XP, Mac OS X
Protocols/Standards/Processors: PCI, PCI-X, PCIE, AMBA AHB, AMBA APB,
AMBA AXI, I2C, SDRAM, 8085, 8086, 8051
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