Design Engineer

********@***.*** • 480-***-**** ****, East University Drive, Tempe, AZ-85281.

Academic Details :

Master of Science Engineering, EE- Mixed Signals (Analog &Digital), Arizona State University –2011 fall to 2012.

B.E in Electrical & Electronics Engineering Anna University, Chennai –2004 to 2008, 75 % (First Class with Distinction)

Academic Projects :

• Engine controller using Cadence: Design and Implemented an Automatic Gear Control Logic design for an Automobile with 12 Cylinder 6 speed Gear and the design was done using transmission, static and dynamic gates in sensing ramp and wind conditions. Power & Speed optimization was done in around 0.5 us Clock Period.

• Comparator Module Design: Design of a 4 bit Comparator and implementing its logic circuit design, and the goal is to achieve the minimum layout area and minimum clock period using Cadence with spectre simulator.

• Traffic Light Design: Creating a Button Handler module that will create useable signals to illustrate user I/O and Finite-State-Machine design that Design of a traffic light control and seven segment module on Xilinx Spartan-3 FPGA and synthesis and simulate using Xilinx ISE 13.3 Simulator.

• Amplifier Design: Design of a Folded Cascode with Class AB Buffer Amplifier Circuit and a Symmetric Operational Transconductance Amplifier using Cadence IC Design tool.

• FIFO Design:Designing an Asynchronous FIFO that can be read from a unit with a slow clock and write from a unit with fast clock and store it in a memory that should be parameterize-able FIFO using Aldec 8.3 Simulators.

• Metastability in FlipFlop: Design and illustrating conditions for Meta-Stability by devise a way to reliably demonstrate meta-stability using Xilinx Spartan-3 FPGA boards and providing technique for solving this problem.

• Design and Testing of 4 Port Switch: Verification based on an online repository for verification concepts in Hardware Design Languages with 4 port I/O switch, whose specifications like packet format & header, Memory Interface and its specifications along with I/O Details using System Verilog.

Subjects Chosen:

Advanced Hardware System Design( Verilog),Advanced Analog Integrated Circuits, VLSI Design, Computer Architecture. Serial Links. Advanced VLSI Design.

Experience

Honeywell Automation India Limited (07-2008 to 04-2010)

Project engineer

• Roles and Responsibilities include design, install and commission of versatile products for integrated building Automation works, tracking of materials from PO release to getting sign off from Client, Client and customer satisfaction and Diplomatic in Maintaining contractors and vendors.

Major Achievements

• Successfully Completed the Project in HCL Campus, Tower1-Jigani Industrial Area, Bangalore and in Areva T&D Centre-Bangalore.

• Completed Six sigma course program both classroom and online.

• Underwent in plant training in Neyveli Lignite Corporation India Limited and Tuticorin Thermal Power Station.

• Done a one year diploma course in Embedded System in Annamalai University.( 06-2010 to 05-2011)

• Completed my master program in Business Administration (E-Business- Correspondence) – Annamalai University.

Undergraduate project: FINGER PRINT BASED SECURITY SYSTEM

Biometric fingerprint security restricts users other than those with registered biometrics for that device from accessing a building, to ensure that only appropriate people can enter a building or room also eliminates the need for users to remember different passwords to gain access saving time and enhancing the user experience

Technical skills Operating Systems : Linux,Windows

Languages : C, C++, Verilog

Simulators : ISE 13.3 & Aldec 8.3 Simulators, Matlab , Spectre , Hspice

Products Tools : Cadence,Xilinx 3 FPGA,EBI 400, DVM 300 & Temaline Solutions.

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