Resume

Sign in

Design Engineer Assistant

Location:
Malkajgiri, Telangana, India
Salary:
10000
Posted:
December 27, 2019

Contact this candidate

Resume:

Page * of *

An enthusiastic and self-motivated experienced Physical design engineer looking for a challenging and responsible position as Physical design engineer to apply my knowledge and skill with my hard work and patience which emphasizes growth, creativity, and analytical thinking. March 2018 to

Present

Aug 2017 to Feb

2018

Aug 2015 to

Jan.2017

July 2011 Aug

2012

Work Experience

Experience : 1 Year 8 months (Physical Design)

Associate Physical Design Engineer

Working in AMD R&D Center India Pvt Ltd, Bangalore as a consultant from Black Pepper Technologies Pvt Ltd.

Experience : 6 months (VLSI Design)

Trainee intern:

CDAC (Centre for Development in Advance computing, Government of India, Pune Associate Software Tester (JSN InfoTech)

Responsibility: -Working as a Trainee with the manual testing and basic knowledge of selenium automated testing.

Assistant Professor (Gokaran Narvadeshwar Institute of Technology & Management) Responsibility: - Specialization subject are Basic Electronics, Digital Electronics. Job

Responsibility

Hands on experience on checking DRC’s in caliber.

Solving congestion issues by keeping blockages.

Realized digital circuits in Verilog using QuestaSim.

Experience in block level tape out including setup, hold, Tran cap fixes.

Excellent understanding of the complete ASIC flow.

Knowledge of CMOS theory and Logic Design and Analog layouts.

Experience in Static Timing Analysis (STA) using PrimeTime tool for analyzing timing reports with OCV, MCMM, CRPR, Clock skew.

Languages and

Tools

Hardware Languages :- Verilog HDL, VHDL

Scripting Languages :- Linux Shell Scripting, Introduction to Perl, TCL

Software Languages :- C, C++, MATLAB

Hardware Description Languages & Associated Tools: Xilinx ISE, Questa-Sim, Model-Sim, Vivado, Micro Magic

Synopsys IC Compiler II, Synopsys PrimeTime, Cadence Innovus, Calibre Education

Diploma in VLSI design, CDAC Pune, secured 78%.

M.Tech (Digital Communication), UPTU, Babu Banarsi Das Northern India Institute of Technology Lucknow, U.P., secured 85%.

B.Tech(Electronics and Communication), UPTU, Prasad Institute of Technology, Jaunpur,U.P., secured 71%

Phone: +91-983*******

Mail: ada5nh@r.postjobfree.com

KAVITA SHARMA

Physical Design Engineer

Page 2 of 3

Project Details

1: Physical Design Implementation of a rectilinear blocks in 7nm TSMC technology. Client : AMD

Role: Tile owner

Description:

Tile1: PD implementation of a rectilinear block on 7 nm process technology, 2 GHz clock frequency. Design consists of 39 macros, 0.86 million standard cells, 11 clocks. Challenges encountered:

1. Placement of macros and reduction of base DRCs. 2. Reduction of Congestion

3. SI, trans, IR violation fixes

4. Improve timing for the design and reduce timing violations. 5. Controlling clock latency for the critical clocks below maximum latency value. 2: Physical Design Implementation of a rectangular Block in 7nm– Training Project

Description: Trained in AMD in l3scDp1Clone block having Macro count-20 and Standard cell count- 69,054.

Trained in AMD TileBuilder Supra flow for Place and Route (PnR) and timing analysis Things Learned:

Understanding the flow and functionality of targets. Understanding the inputs and outputs for each targets of Floorplan, Placement, CTS, Routing etc., Debugging causes for target failures.

Starting branches and parallel runs. Knowledge on params, controls, tune files required during flow execution.

PnR:

Changing the location of placed macros through tune TCL files. Go through the command files for PnR targets and understand the functionality of important commands and overall understanding on what actually happens during each stage. Analyze the various reports like qor, utilization, timing, congestion, DRCs and decide on the further actions required to improve the design. Debug the log file for issues during each stage.

Page 3 of 3

Tool: Getting familiarized with Synopsys ICC2 & PrimeTime tool and caliber. 3: CDAC project : Implementation and Verification of AXI4-Lite Duration : December 2017- January 2018

HDL language : Verilog HDL

Tool: xilinx ISE, Questa sim

Description:

The ARM has developed AMBA bus protocolwhich is widely used by SoCdesigners. It supports the efficient connection of processors, on-chip memories and off-chip external memory interfaces. AXI Interconnect provides efficient connection between master and slave with high-performance & high-frequency of operation. Projects During

Course

M.Tech project

Performance improvement of SC-FDMA using IFDMA and LFDMA Tool used: MATLAB

Description:

Single carrier frequency division multiple access (SCFDMA) is a new multiple access technique that utilizes single carrier modulation, DFT- spread orthogonal frequency division multiplexing and frequency domain equalization. It has similar structure and performance as OFDMA. SC-FDMA is currently adopted as the uplink multiple access schemes for 3GPP

(Third Generation Partnership Project) LTE (Long Term Evolution). The major reason for PAPR in OFDM is its multi-carrier structure.

Additional

Achievements

GATE qualified in 2019, 2014 and 2011.

Participated in National Level Science Exhibition program. Selected as a student coordinator throughout BTech course. Personal Information:

Present Address: Saanvi PG for ladies, 6th main, BEML layout, opposite of AECS layout, kundanahalli gate, Bengaluru, Karnataka – 560037

Permanent Address: SC-3A, Basant lane, near railway hospital, New Delhi - 110001 Date of birth: 1991-06-14

Marital Status: Single

Languages Known: Hindi and English

Nationality: Indian

Email Address: ada5nh@r.postjobfree.com

LinkedIn Id: - https://www.linkedin.com/in/kavita-sharma-a0b713152/ Declaration:

I hereby declare that the above mentioned information is correct up to my knowledge and I bear the responsibility for the correctness of the above mentioned particulars. Place: Bengaluru Kavita Sharma



Contact this candidate