Flat No: ***, MMR Residency Apartments,

Shalivahana Nagar, Dilsukhnagar, Hyderabad - 500060

+91-701*******

ada63v@r.postjobfree.com

www.linkedin.com/in/buramdeepak

BURAM DEEPAK YADAV

CAREER OBJECTIVE To obtain a challenging position in the field in addition to contributing significantly to the organization. I would be able to hone my skills in an enriching environment. Looking for an opportunity to work in your estimated organization where I can enhance my skills and experience.

PROFESSIONAL TRAINING An Industry Oriented Trainee in VLSI Design and Verification from Moschip Institute of Silicon Systems Pvt Ltd., (M-ISS) Hyderabad.

Course Outline:

VLSI Fundamentals, Digital Designs on Combinational and Sequential, Designs using FSM approach, Verilog, System Verilog, Coverage based Verification, Assertion based Verification, UVM Methodology, Verification Plan, Regression, Up-Down Counter with Internal Registers, APB protocol, SPI Protocol.

EDUCATION DEGREE COLLEGE YEAR SCORE

B.Tech

(E C E)

Sri Indu College of Engineering

and Technology

2015-2019 65.24%

Intermediate Sri Gayatri Junior College 2013-2015 79.80% S.S.C Dilsukhnagar Public School 2012 85.00%

TECHNICAL EXPERTISE HDL : Verilog

HVL : System Verilog

Test bench Methodologies : UVM

Verification Methodologies : Coverage Driven Verification, Assertion Driven Verification Tools : Cadence (NCSim & SimVision), IMC, Aldec Riviera Pro Domain : ASIC/FPGA front-end Design and Verification Knowledge : RTL Coding, FSM based Design, Coverage driven, Assertion based Verification

PROJECT DETAILS PROJECT1: Synchronous Up-Down Counter with Internal Registers- Design & Verification Description: The Up Down Counter contains four registers to load preload, upper limit, lower limit and cycle count which can select based on selection lines and starts counting by start pulse from preload to upper limit after reaching upper limit count downs to lower limit and stops counting once it reaches the cycle count. Role: Designing RTL code according to the specification, Architected the class-based verification environment in SV and UVM, Verified RTL module using SV, Generated Assertion based Verification and Generated functional and code coverage for the RTL verification signoff.

PROJECT 2: APB PROTOCOL - Verification

Description: APB is used as an interface for any peripheral that are low-bandwidth and do not require the high performance of a pipelined bus interface. It provides a low-cost interface that is optimized for minimal power consumption and reduced interface complexity.

Role: Defined verification plan, Architected the class-based verification environment in SV and UVM, Verified RTL module using SV and Generated functional and code coverage for the RTL verification signoff.

PROJECT 3: APB-SPI BRIDGE - Verification

Description: APB SPI Bridge is meant to be interfaced with slow speed peripherals. APB slave initiate the transaction which can read data from write data to SPI peripheral. Since SPI is serial interface, the design will ensure that data transmitted to or received from SPI interface before it initiates a new transaction.

Role: Defined verification plan, Architected the class-based verification environment in SV and UVM, Verified RTL module using SV and Generated functional and code coverage for the RTL verification signoff.

ACHIEVEMENTS • Received a certificate from "MANIPAL UNIVERSITY" for the active and in valuable participation in LEVEL-1 of Teenovators in National level championship.

• Received a certificate as "WINNERS" in the school wise tournaments.

• Received a certificate in a "DOUBLE CLICK" program for computer education. ASSETS • Enthusiastic worker in a team.

• Dedicated, Determined and Disciplined worker.

• Good Analytical skills.

• Positive Attitude.

• Good presentation and Communication skills.

PERSONAL DETAILS Name : Buram Deepak Yadav

Father’s Name : B. Balraj

Date of Birth : 15-May-1998

Nationality : Indian

Current Location : Hyderabad, India

Languages Known : English, Hindi, Telugu

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