| Resume alert | Resumes 1 - 10 of 73 |
Scrum Master Business Development
Pflugerville, TX
... GRADUATE COURSEWORK, September 2010 – May 2010 Digital Systems and Logic Design, MATLAB, computer architecture, advanced digital IC design (VHDL, VLSI, and FPGA) HONORS ●Participated in paper presentation on Software Development Life Cycle in ... - Apr 12
... GRADUATE COURSEWORK, September 2010 – May 2010 Digital Systems and Logic Design, MATLAB, computer architecture, advanced digital IC design (VHDL, VLSI, and FPGA) HONORS ●Participated in paper presentation on Software Development Life Cycle in ... - Apr 12
Software Engineer Senior
Austin, TX
... (https://github.com/mlshort/AssocDataCache) • Research involved P4 (https://p4.org/), P4FPGA and Microsoft’s Catapult FPGA project, in conjunction with the University of Texas at Austin. (Microsoft Project Catapult). Involved installation, ... - Jan 14
... (https://github.com/mlshort/AssocDataCache) • Research involved P4 (https://p4.org/), P4FPGA and Microsoft’s Catapult FPGA project, in conjunction with the University of Texas at Austin. (Microsoft Project Catapult). Involved installation, ... - Jan 14
Electrical Engineer Engineering
Pflugerville, TX
... • Harmonic & Power Quality • Protection & Coordination • Automation Controls • Robotics • Distance Relays • Solar and WTG • FPGA • eTraX Software/Communication Protocols: • ETAP • Altium Designer • Revit • PSS-E • Anova • DOE • AutoCAD/CAM • PSCAD • ... - Jan 03
... • Harmonic & Power Quality • Protection & Coordination • Automation Controls • Robotics • Distance Relays • Solar and WTG • FPGA • eTraX Software/Communication Protocols: • ETAP • Altium Designer • Revit • PSS-E • Anova • DOE • AutoCAD/CAM • PSCAD • ... - Jan 03
Team Lead Rtl Design
Austin, TX
SRINIVAS KUMAR CH Skilled and accomplished Senior RTL Engineer with 15+ years of experience in FPGA/ASIC front end design. Good Experience in FPGA design flow, validation and System level debug. Lead CDC teams to accomplish two SoC sign offs for ... - 2023 Jul 12
SRINIVAS KUMAR CH Skilled and accomplished Senior RTL Engineer with 15+ years of experience in FPGA/ASIC front end design. Good Experience in FPGA design flow, validation and System level debug. Lead CDC teams to accomplish two SoC sign offs for ... - 2023 Jul 12
Business Analyst Event Manager
Leander, TX
... Used a MPC8260 processor and Xilinx Spartan II FPGA for control of serial EPROM, temperature sensors, status & control registers, and Fast Ethernet transceiver. Designed Circuit Card Assembly (CCA) to interface with FPGA DeinterLeaver/Decoder CCA ... - 2023 May 06
... Used a MPC8260 processor and Xilinx Spartan II FPGA for control of serial EPROM, temperature sensors, status & control registers, and Fast Ethernet transceiver. Designed Circuit Card Assembly (CCA) to interface with FPGA DeinterLeaver/Decoder CCA ... - 2023 May 06
Electrical Engineer Research Assistant
Austin, TX
... Python • Microprocessors & Microcontrollers • Instrumentation and sensors with LabView as main software • VLSI and FPGA Programming • Biomedics for engineers • Networking & industrial networking • Communication systems • PLC and industrial ... - 2023 Jan 13
... Python • Microprocessors & Microcontrollers • Instrumentation and sensors with LabView as main software • VLSI and FPGA Programming • Biomedics for engineers • Networking & industrial networking • Communication systems • PLC and industrial ... - 2023 Jan 13
Research Assistant Development Engineer
Austin, TX
... on architecture and performance Coordinated and conducted debug sessions with di erent device vendors (NIC, NVMe SSD, GPU, FPGA), identi ed opportunities for performance improvement, and ensured their implementation Dell Austin, TX Senior Sta HPC ... - 2021 Jul 05
... on architecture and performance Coordinated and conducted debug sessions with di erent device vendors (NIC, NVMe SSD, GPU, FPGA), identi ed opportunities for performance improvement, and ensured their implementation Dell Austin, TX Senior Sta HPC ... - 2021 Jul 05
Designer Controller
Austin, TX
... SKILLS General Programming : C, C++11, Java9, C#/WPF ASIC/FPGA Modeling : Verilog, Vhdl, System Verilog ASIC Synthesis : Synopsys, Synplify, Primetime, STA, 0-in, CDC FPGA Design : Xilinx, ISE, Vivado, Altera, Quartus, Qsys, Virtex, Spartan, ... - 2021 May 20
... SKILLS General Programming : C, C++11, Java9, C#/WPF ASIC/FPGA Modeling : Verilog, Vhdl, System Verilog ASIC Synthesis : Synopsys, Synplify, Primetime, STA, 0-in, CDC FPGA Design : Xilinx, ISE, Vivado, Altera, Quartus, Qsys, Virtex, Spartan, ... - 2021 May 20
Engineer
Austin, TX
... Stack instructions • Micro-Processor programing and testing (x86, ARM, MIPS) • Lab equipment: Oscilloscopes, Multi-meters, FPGA board, Logic analyzer • Projects: Raspberry Pi Cluster (wireless protocols, TCP/IP, C programing and testing) • Knowledge ... - 2020 Apr 08
... Stack instructions • Micro-Processor programing and testing (x86, ARM, MIPS) • Lab equipment: Oscilloscopes, Multi-meters, FPGA board, Logic analyzer • Projects: Raspberry Pi Cluster (wireless protocols, TCP/IP, C programing and testing) • Knowledge ... - 2020 Apr 08
Product Marketing, Channel Marketing, Sales Enablement
Austin, TX, 78739
... • Made executive decision to withdraw platinum sponsorship from Xilinx X-Fest FPGA event. Decision saved Freescale $1M. Reallocated these funds to demand creation programs that delivered higher field impact. • Launched Avnet Make The Move To ... - 2019 Dec 25
... • Made executive decision to withdraw platinum sponsorship from Xilinx X-Fest FPGA event. Decision saved Freescale $1M. Reallocated these funds to demand creation programs that delivered higher field impact. • Launched Avnet Make The Move To ... - 2019 Dec 25