Bill Moore

571-***-****

Present Location: VA-MD-DC

Email: admk4t@r.postjobfree.com

Computer and Electrical Engineering

ASICs, FPGAs, DSPs, Software

SUMMARY

Computer architecture, logic design, synthesis, timing closure, system level integration.

Implementation of logic for digital communications, dsp, network protocols, high-speed buses, and microprocessors.

Software development for embedded devices and cpu boards, software for linux drivers and baremetal drivers, software for hardware testing and verification, and software for diagnostic.

SKILLS

General Programming : C, C++11, Java9, C#/WPF

ASIC/FPGA Modeling : Verilog, Vhdl, System Verilog

ASIC Synthesis : Synopsys, Synplify, Primetime, STA, 0-in, CDC

FPGA Design : Xilinx, ISE, Vivado, Altera, Quartus, Qsys,

Virtex, Spartan, Stratrix, ARM SOC Integration

Debug : Modelsim, Questa, Cadence, SimVision, Vcs,

ChipScope, SignalTap

Board Design : Altium, Orcad

Scripting : Perl, Python, tcl, bash, csh, php, sql, javascript, cms

GUI Programming : C#/WPF/XAML, C++/GTK+/gtkmm, C++/Qt, Java

DSP/Algorithms : Matlab, Octave, Python, NumPy, SymPy, MatPlotLib, Jupyter Notebooks

WORK HISTORY

04/2004 to present Freescale Semiconductors Austin, TX

ASIC Designer

Hardware design and veification of IC chipsets for wireless communications.

Design and Implementation of digital baseband in wireless modem, specifically, the Viterbi and channel coding error correction system, encryption and decrytion unit, and link layer logic.

Worked closely with system designer to convert matlab and C++ models to SystemVerilog.

FEC system fully Verified from system level to RTL code, including 660 Mbit/sec Viterbi decoder, interleavers, Rate Adaptive Puncture Unit, BER measurement unit, and Packet Framer.

Design and Implemented 1.0 Gbits/sec CCM Encryption / Decryption engine. This design was composed of two AES code-book encryption processors, a register file for configuring the Nonce and Key, authentication and encryption fifos, and a DMA engine. The first code-book encryption processor was configured to perform CTR encryption/decryption; the second processor was configured to perform CBC authentication and Message Integrity code generation.

Synthesized and gate-level debug.

Implemented DDR3 behavioral phy model for 1.5 Ghz Memory controller.

11/1999 to 04/2004 Cadence Chelmsford, MA

ASIC Designer

ASIC design & verification consultant.

Responsibly for setting up and maintaining ASIC simulation and emulation testing environments for Cadence EDA tools related to hardware accelleration and emulation.

10/1998 to 11/1999 Sarnoff Digital Communications Newtown, PA

ASIC Designer

Hardware design and verificationt of digital television receiver IC chips for high defition TV sets and receivers.

Logic design for QAM and VSB wireless modem standards.

Implemented and verified logic for advanced DSP algorithms.

05/1996 to 10/1998 IBM Microelectronics Burlington, VT

ASIC Designer

Hadware design and verification of a microprocessor IC chips, specifically, an unlicensed clone of the ARM7, and Texas instruments C54x DSP that were create from scatch without using Texas Instruments and Arm’s intellectual property. This is similar to the way that AMD and Intel produces competing x86 microprocessors.

Verification and Design of DSP microcode, including: debugging of DSP microcode, and implemention of changes to reduce power consumption.

Verilog testbench and scripts for loading testcases into Hardware cpu model, and checking of results. collect regression data, and launching of regression test suites.

EDUCATION

West Virginia University

Morgantown, WV

BS Computer Engineering, 1996

BS Electrical Engineering, 1996

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