SRINIVAS KUMAR CH

Skilled and accomplished Senior RTL Engineer with 15+ years of experience in FPGA/ASIC front end design. Good Experience in FPGA design flow, validation and System level debug. Lead CDC teams to accomplish two SoC sign offs for INTEL client. Experience in building teams, interacting with customers and third party vendors. Received excellence awards for the years 2018,2019 and 2007 for good performance and leadership roles.

Technical skills and Tools

Very Good

Coding Languages: Verilog HDL, VHDL, System Verilog, C Very Good

ASIC/FPGA tools – Design compiler, Protocompiler, Spyglass CDC, Spyglass Lint,Model Sim, Questa sim, veloce,Lintra Lint, Questa CDC, Zebu compiler, Conformal LEC, Power Artist,Xilinx ISE, Xilinx Vivado, Chipscope, Microchip Libero, Altera Quartus 2. Good

Protocols: Ethernet, SPI, I2C, AXI, AHB, PCIe, WiFi Good

Scripting Languages: Perl, Python, Tcl

Good

Operating System: Linux, Solaris

Good

RISC processor design as my B.Tech project

Work History

Aug 2009 -

Current

Senior RTL engineer

Cerium Systems, San Jose, USA

Designed and accomplished the entire FPGA flow activities of GBSL3-IS module for ASML cleint. Activities include design document creation, VHDL coding, test case creation and simulation, timing analysis, CDC, synthesis and validation targeting Microchip Smart fusion 2.Python scripting is done for Senior RTL Engineer

Address Austin, TX, 78713

Phone 978-***-****

E-mail adx84l@r.postjobfree.com

validating the design on PCB.

Accomplished the design changes to the existing AXE Wi-Fi module for Keysight client, did System Verilog coding, timing analysis, debug, testbench design and development.

Designed the GNSS module for Keysight client. Accomplished the role of team, Design spec discussions, Design document creation, Design partitioning and assigning tasks to team members. RTL coding in VHDL, Defining test procedures, Simulation and FPGA testing.

Accomplished the team Lead role by signing off MGR SoC for Intel client, worked on setting up Synopsys Spyglass tool flow environments, generating abstracts, constraints, cleaning up the flow, report analysis, debugging and adding waivers.

Accomplished the role of team lead to sign off TNR SoC for Intel Client, worked on setting up Synopsys Spyglass tool flow environments, generating abstracts, constraints, cleaning up the flow, report analysis, debugging and adding waivers.

Built and lead the team from cerium systems for Intel client, activities include Constraints setting, cleaning up the team, activities include Constraints setting, cleaning up the flow, report analysis, debug and setting up tool flow environments. Tools include Spyglass (lint, Spyglass CDC, spyglassLP, SpyglassDFT), Design compiler, Veloce, zebu compiler, synopsys protocompiler, Conformal LEC, Calibre, Power Artist, Lintra lint, Questa CDC. Done the coding, simulations, synthesis, Spyglass CDC in designing and implementing SNR block as a part of Intel trace NoC development. Designed, coded and implemented Data Path FPGA and IO FPGA for CISCO Routing System. Activities include requirements capture, design implementation, verification, timing closure, integration/test and design release. Worked independently in resolving the customer issues. Communicated effectively with other teams in CISCO. Designed, coded and implemented IO FPGA and Data Path FPGA for Titano series Line card project for CISCO client.

Consistently worked on debugging and troubleshooting issues affecting product level for Titano series projects. Investigated and resolved customer issues independently, done system level debug.

Part of the team that developed Deep sleep controller IP for 28 nm virage RAMsIP Module Design for PMC Sierra client. Activities include RTL design and development, testcase development, Spyglass Lint, Static timing analysis. RTL design and development for AXI protocols, worked closely with verification team to verify the design thoroughly. worked on closed to develop contour object recognition algorithm Aug 2006 -

Aug 2009

Project Engineer

Wipro Technologies, Hyderabad, Telangana, India

Motorola LTE project activities include Converting the schematics into the Verilog code. Done simulations and testing on FPGA.This is a 3G mobile communication modem which is designed to operate based on long term evaluation algorithms according to 3GPP specification. Configured and generated the SerDes IP, generated the power estimation logic and test vectors to estimate the dynamic power in simulations. Tested the same on FPGA. This Quad Modem Logic Baseboard (QMLB) system consists of 4 Stratic III FPGAs which emulate approx 8M ASIC gates. This system is developed to support LTE algorithm development. Designed and implemented the bridge, between the AVALON core and DDR2 IP controller, The bridge converts the data and control signals from 150 MHz to 333 MHz and Vice versa.

Video Mux module works as a multiplexer for the incoming video data from 8 channels on to two output channels. The incoming video data is stored in a DDR2 Memory and then retrieved for multiplexing. This module works at 125 MHz frequency. My activities include RTL coding for sequencer block and clock control block, synthesis, PAR and STA for the design, FPGA fitting, verification and validation.

Education

Aug 2004 -

Jul 2006

M.Tech: VLSI

JNTU - Hyderabad

Pass Percentage: 80%

Aug 2000 -

Jun 2004

Bachelor of Technology: ECE

JNTU - Hyderabad

Pass percentage: 70%

Accomplishments

Awards for good performance in the years 2018 and 2019 at cerium systems. Trail blazer award for my first project in WIPRO.

All India 2800 Rank in GATE with 94.8 percentile.

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