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Resumes 61 - 70 of 229 |
Santa Clara, CA
... EXPERIENCE: ASSEMBLY, 6/2017-PRESENT, FINISAR CORP Final assembly including, die attach, wirebond, cap seal, leak check. FAB OPERATOR, 10/2016-6/2017, WESTERN DIGITAL Fab operator METAL/TFILM area, certified BALZERS CORONA sputter. FAB OPERATOR, 11 ...
- 2018 Jan 09
Los Altos, CA
... ● Machine learning models of Apple memory, BICS3 reliability, die sort parameters tuning(LASSO, XGBoost, Ranger) ● ML performance a deep analysis of the HTPD/RTPD/LTPD test data to define a model of FBC growth rate across the temperature. ● Memory ...
- 2017 Dec 29
San Jose, CA
... 8 Equipment Engineers, 7 Equipment Techs o7 years Manager, Test Engineering Deliver electrical testers for wafer/rowbar/die level TEL/Electroglas/Hitachi-Deco/Phasemetrics/In-house developed equipment 4 Programmers, 2 M.E.’s, 3 E.E.’s, 1 Device ...
- 2017 Nov 02
Milpitas, CA, 95035
... Presented an idea of a new die design to reduce material loss by 20 percent as well as reduce process time by 30 seconds. Mechanical Engineering Intern, Greaves Cotton Pvt. Ltd., India. (2 months) June13-July13 Greaves Cotton is one of the biggest ...
- 2017 Aug 24
San Jose, CA
... Leader in the development of other types of packages using metal leadframe or laminate (ceramic or PCB) with thermal dissipation consideration,..QFN, COB, Chip scale, SiP, WLP, stacked die, MEMS/MOEMS, Laser projection module and flip chip (FC) with ...
- 2017 Aug 07
Fremont, CA
... QUALCOMM - STRATEGY San Diego, CA Marketing Manager December 2006-February 2008 • Performed Bill-of-Material and die cost analysis for various wireless and computing devices (smartphones, data cards, navigation devices, consumer devices). Created ...
- 2017 Aug 04
San Jose, CA
... • Develop and implemented pre-silicon die and power estimates for the IOs, memories and random logic power for 90nm and 65nm process nodes. • Evaluated vendors and foundries with low power libraries, memories and IOs with leakage and standby power ...
- 2017 Jul 19
Sunnyvale, CA, 94087
... Perform Die-Attach and Tip Attach. Perform set up, calibration and preventive maintenance task on test stations. Perform Pre-test, Tension, Temperature Cycle, Temperature Compensation, Jitter, Stressed Sensitivity, EEPROM and Final-test for the 30, ...
- 2017 Jun 26
Sunnyvale, CA, 94089
... • Problem Solving: Reduced production duration for card boxes from 50 days to 30 days by re- designing a creative die line to reduce manual assembly work. The deadline achieved and saved 30% of labor costs. • Eco friendly/Cost optimization: Saved ...
- 2017 Jun 22
San Jose, CA
... Inspected and analyzed first level operational defect inspection data for lab materials using Die-attach and Performed saw (dies singulating) INTERSIL CORP. Milpitas, CA 02-2005/12-2010 Reliability Test Tech: Performed routine tests and trouble ...
- 2017 Jun 20