| Distance: | Resume alert | Resumes 301 - 310 of 7160 |
Digital Marketing Sales Manager
Lisle, IL, 60532
... ● Championed performance-based culture with strong accountability, pipeline hygiene, and cadence-based coaching across distributed teams. ● Launched and scaled BD/MD Agency Model across North America, reviving dormant SMB accounts and increasing rep ... - 2025 Jul 06
... ● Championed performance-based culture with strong accountability, pipeline hygiene, and cadence-based coaching across distributed teams. ● Launched and scaled BD/MD Agency Model across North America, reviving dormant SMB accounts and increasing rep ... - 2025 Jul 06
Design Engineer Circuit
San Jose, CA
... Languages: IBIS models, Verilog-A, HSpice, Python, Ocean scripting, TCL scripting, MATLAB, C, C++ Software: Cadence Virtuoso (ADE XL, Maestro, Layout XL), Ansys Totem, Ansys Helic, Matlab, Hspice, Cadence Allegro, JMP, Logisim, Avanwaves, Cosim ... - 2025 Jul 06
... Languages: IBIS models, Verilog-A, HSpice, Python, Ocean scripting, TCL scripting, MATLAB, C, C++ Software: Cadence Virtuoso (ADE XL, Maestro, Layout XL), Ansys Totem, Ansys Helic, Matlab, Hspice, Cadence Allegro, JMP, Logisim, Avanwaves, Cosim ... - 2025 Jul 06
Software Engineer Linux Systems
Gilbert, AZ
... SunOS, Solaris, Windows XP, Macintosh OSX, AIX CAD Engineering Applications: TCAD, ICCAP, SPICE like simulators, ADS, ANSYS, Cadence, Synopsys, Mentor PROFESSIONAL EXPERIENCE Intel, Mesa, AZ (remote) Design Automation Engineer - Development Tools ... - 2025 Jul 05
... SunOS, Solaris, Windows XP, Macintosh OSX, AIX CAD Engineering Applications: TCAD, ICCAP, SPICE like simulators, ADS, ANSYS, Cadence, Synopsys, Mentor PROFESSIONAL EXPERIENCE Intel, Mesa, AZ (remote) Design Automation Engineer - Development Tools ... - 2025 Jul 05
Design Engineer Applications
Cupertino, CA
... Performed simulations using HSPICE and Spectre, schematic capture, layout with Cadence Virtuoso (contractor), hardware testing. 1/00-4/03: National Semiconductor, Santa Clara, CA Design Engineer, worked on design of ESD circuits and CMOS I/O buffers ... - 2025 Jul 04
... Performed simulations using HSPICE and Spectre, schematic capture, layout with Cadence Virtuoso (contractor), hardware testing. 1/00-4/03: National Semiconductor, Santa Clara, CA Design Engineer, worked on design of ESD circuits and CMOS I/O buffers ... - 2025 Jul 04
Product Owner Systems Analyst
Santa Clara, UT, 84765
... • Improved and streamlined product backlog for work deliverables with team, establishing regular delivery cadence on releases and working at 90% capacity. • Collaborated with internal and external stakeholders on the transition of 2.2M members from ... - 2025 Jul 04
... • Improved and streamlined product backlog for work deliverables with team, establishing regular delivery cadence on releases and working at 90% capacity. • Collaborated with internal and external stakeholders on the transition of 2.2M members from ... - 2025 Jul 04
Ts Sci Mixed Signal
San Jose, CA
... ● Proficient in using Mentor Graphics/ Siemens and other EDA industry-standard tools for verification and Cadence, Synopsys electronic design automation tools. SKILLS: ● ● Neuromorphic processors Intel power/instruction optimization ● API, HPS, OS, ... - 2025 Jul 04
... ● Proficient in using Mentor Graphics/ Siemens and other EDA industry-standard tools for verification and Cadence, Synopsys electronic design automation tools. SKILLS: ● ● Neuromorphic processors Intel power/instruction optimization ● API, HPS, OS, ... - 2025 Jul 04
Scrum Master Business Analyst
Atlanta, GA
... • Facilitated workshops on backlog creation, hypothesis testing, and iterative delivery, driving a 40% rise in product launch cadence. CareFirst BlueCross BlueShield — Product Owner Mar 2019 – Sept 2021 • Owned and prioritized product backlog for ... - 2025 Jul 03
... • Facilitated workshops on backlog creation, hypothesis testing, and iterative delivery, driving a 40% rise in product launch cadence. CareFirst BlueCross BlueShield — Product Owner Mar 2019 – Sept 2021 • Owned and prioritized product backlog for ... - 2025 Jul 03
Regional Sales Senior Director
Milpitas, CA
... Solution Specialists, Global POD Leader (Sr Director) - EDA / Semiconductor Accounts Managed 30+ Global EDA Semiconductor Accounts: Key clients include Nvidia, Intel, Marvell, Micron, Broadcom, Fortinet, Western Digital, Cadence Design, and Qorvo. ... - 2025 Jul 03
... Solution Specialists, Global POD Leader (Sr Director) - EDA / Semiconductor Accounts Managed 30+ Global EDA Semiconductor Accounts: Key clients include Nvidia, Intel, Marvell, Micron, Broadcom, Fortinet, Western Digital, Cadence Design, and Qorvo. ... - 2025 Jul 03
Enterprise Solutions Business Process
Fairview, TX
... Cadence Bank - BAMOE Implementation and DevOps Modernization Architected and led the implementation of Business Automation Manager Open Editions (Kogito), driving business process automation adoption. Modernized salesforce to cloud-native, event ... - 2025 Jul 02
... Cadence Bank - BAMOE Implementation and DevOps Modernization Architected and led the implementation of Business Automation Manager Open Editions (Kogito), driving business process automation adoption. Modernized salesforce to cloud-native, event ... - 2025 Jul 02
Software Engineer Node Js
Queens, NY
... ● Facilitated Agile ceremonies including sprint planning, demos, retrospectives, and daily standups to maintain team cadence. ● Defined and enforced change control policies for releases, preventing scope creep and cutting regression risk across ... - 2025 Jul 02
... ● Facilitated Agile ceremonies including sprint planning, demos, retrospectives, and daily standups to maintain team cadence. ● Defined and enforced change control policies for releases, preventing scope creep and cutting regression risk across ... - 2025 Jul 02