Design Engineer Business Development

Bret Raymis

Yuma, AZ

**********@*****.*** M 858-***-****

SUMMARY:

• Highly accomplished Mask Layout Design Engineer with years of experience delivering complex IC layouts from concept to tape-out across analog, digital, mixed-signal, RF, and PMIC designs.

• Demonstrated ability in layout floor planning, standard cell design, hierarchical layout assembly, device matching, shielding and guard ring implementation, DFM optimization, as well as GDSII and E-beam mask generation.

• Capable of successful digital place-and-route for large-scale designs and leading back-end teams, supervising up to twenty-five designers across multiple concurrent projects.

• Extensive background in advanced technology nodes including IBM 5–7nm, Samsung 10–14nm FinFET, TSMC 65– 20nm FinFET, and legacy nodes down to 130nm.

• Skilled in Cadence Virtuoso, Innovus, Mentor Calibre, Synopsys Compiler, and industry-standard verification flows

(DRC, LVS, LPE).

• Produced over fifty successful chip tape-outs with exceptional quality, area efficiency, and on-time execution.

• Recognized for debugging complex PDK flows, developing innovative physical design kits, and mentoring engineers to meet aggressive timelines.

• Holds Secret-level security clearance and excels in both remote and onsite environments, with strong problem- solving, analytical, and business development capabilities to drive innovation in semiconductor design. TECHNICAL SKILLS & TOOLS:

• Platforms: Unix/Linux Redhat, Netlists, Microsoft Office.

• Spectrum Internet: Typical download speeds 500MBps. Available 1to 3 GBps

• Tools: Specialize in Cadence 6.1 Virtuoso VX, First Encounter, Innovus, Assura, PVS, Mentor Calibre, Synopsys Compiler

• Technologies: IBM 5-7 nm, Samsung 10-14 nm FinFet, TSMC 65-20 nm FinFet, TSMC/GF 40-130 nm, XFAB XT018

• Hardware and environment: 37 inch monitor, ASUS Vivobook i9 processor, laptop, private office, VPN with ID

• Media: Zoom, Google Meet, or Microsoft Teams

PROFESSIONAL EXPERIENCE:

Career break July 2023 – Present

• After layoffs at Apex, I took time off for family and volunteering

• Available and actively looking for remote work

APEX Semiconductor, Raleigh, NC Jan 2023 – June 2023 ASIC Layout Engineer III

• Lead on LIN block in XFAB XT018 process

• Instrumental bringing up the complex PDK flow for high voltage SOI process

• Completed final dummy fill for zero density issues Numem, San Jose, CA Aug 2022 – Oct 2022

Physical Design Engineer

• Verification of main core memory design using Synopsys Custom Complier in TSMC 22 nm

• Documentation on Windows to Synopsys, density fill, DRC, LVS and LPE flows Raytheon, El Segundo, CA Oct 2021 - Aug 2022

Layout Engineer

• Assigned to design 40 GHz ADC, DAC, and SERDES in GlobalFoundries SOI 45 nm

• Layout and schematics on core cell for regulator with bipolar devices. Draper Labs, Cambridge, MA Sep 2020 - Sep 2021

Layout Engineer

• Assigned to design a mux & sensor block in GlobalFoundries 12LP in 6 weeks while mentoring a junior engineer

• Lead layout engineer in Intel 22ffl process for secret project creating vref, high performance amps, bandgaps, sensors, muxes, and switch blocks

IBM, Yorktown, NY July 2019 – Nov 2019

Design Aid/Senior Layout Contractor

• Remotely supported the Zurich, Switzerland group doing bottom to top level memory arrays on AI project

• Samsung 14 nm FinFet with twenty levels of metal Covalar Design, Richardson, TX Apr 2019 - May 2019 Senior Layout Contractor for L3T, Plano, TX

• Only a 5-week contract for night vision circuits in TowerJazz 13 nm

• Assigned the ADC overly complex 12-micron wide column decoder with mirrored logic without matching schematics Lockheed Martin, Moorestown, NJ Sept 2018 – Dec 2018 Senior Layout Contractor

• Lead designer on 18GHz RF LNA analog circuits in SIGE 90nm, 10-metal Global Foundries process

• Laid out a 4-stage amplifier

• Extraction of the amplifier compared excellent to circuit simulations on first pass IBM, Armonk, NY Apr 2018 - Sept 2018

Senior Layout Contractor

• Remote layout on macro devices below 7nm in joint technology by Samsung, Global Foundries, and IBM

• Communicated with seven (7) different engineers on twelve (12) different layout designs from around the United States

Micron Technology, Minneapolis, MN Feb 2018 - Apr 2018 Senior Layout Contractor

• Layout on GHz ASIC delay logic in TSMC 28nm process ARM, Deerfield Beach, FL Aug 2017 – Sept 2017

Senior Layout Contractor

Layout of Bluetooth bias LDO block in TSMC 40/45nm process Ambiq Micro, Austin, TX May 2017 - Aug 2017

Lead layout Designer

• Lead designer an ultra-low power RF 40/45nm ultra-low power TSMC process Synapse Design, Santa Clara, CA Dec 2016 – Mar 2017 Senior Layout Contractor for Skyworks, Woburn, MA

• Responsible for entire analog and digital part of chip in IBM/Global Foundries SOI process

• Porting and shrinking analog switches, voltage regulators and LDOs from IBM to TSMC SOI 11nm process Synapse Design, Santa Clara, CA Aug 2016 – Sept 2016 Senior Layout Contractor for Intel, Chandler, AZ

• Laid out connections on a top-level analog block in TSMC 28nm for a 5G RF chip

• Worked closely with chip lead designer in verifications of DRC, LVS, VMSLAY and interpreting the results Qualstaff, San Diego, CA May 2016 – July 2016

Senior Layout Contractor for Peregrine Semiconductors

• Lead person for LNA RF chips

• Floor planned and instructed other personnel on layout netPolarity - San Jose, CA Feb 2016 – Apr 2016

Layout Contractor for Rambus

• Completed an extraordinarily complex high-speed 30GHz transceiver block in Samsung 14nm in just three months Qualcomm - San Diego, CA May 2011 – Nov 2015

Senior Mask Layout Designer

• Lead for DDR 2.0 and 2.5 blocks currently in Snapdragon 810 processor

• Completed the layout of analog LDO and op amps blocks for SerDes

• Main physical designer driving place-and-route Cadence First Encounter for ten (10) DDR control blocks

• Lead designer on PMIC for James Doyle creating large power transistors and top-level plan.

• Led an international team on a bandgap and PLL transceiver using Samsung 10nm FinFET for Snapdragon 835 EDUCATION & OTHER TRAINING:

• Attended Montgomery Community College for one year, Montgomeryville, PA

• US Army Avionics technician with 101st Airborne Division, Medevac unit at Fort Campbell, KY PROFESSIONAL ASSOCIATION & BOARD POSITIONS

• Active member of Yuma Crossings Rotary since 2014

• Active member of Yuma Elks Lodge #476 since 2021

• Board Member, "I Love a Clean San Diego" (2012-2014)

• Board Member, Palm Schwenkfelder Church, Palm, PA

• Founder and President, Big Country Neighborhood Association

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