San Antonio, TX
... SENIOR PROJECT MANAGER Cadence McShane Construction, San Antonio, TX (2021-2023) Hired to steer the progression of $70M multi-family projects, leading all components of contract writing, scope review and scheduling. Stepped into role upon departure ...
- Jul 07
Austin, TX, 78746
... • Partnered with senior leadership to drive operational cadence, improve collaboration, and identify opportunities for digital transformation. • Program Manager, 03/2018 to 05/2022 Apple – Austin, TX Managed large-scale global programs that ...
- Jul 07
Pittsburgh, PA
... 2 Skills SPIN – BANT – Salesforce – Negotiation – Maintaining Pipeline – CRM Management – Cadence – B2B Sales – Prospecting – Product Presentation – Organizational Structure – Pre-sales – Technical Assistance – Technical Solutions Certificates Act ...
- Jul 06
Lebanon, TN
... Championed Agile adoption among infrastructure teams to improve delivery cadence and customer satisfaction. Planned and held weekly projects and sprint meetings and backlog grooming. April 2017 – August 2018 PNC Bank & Financial Services Sr. IT ...
- Jul 06
Lisle, IL, 60532
... ● Championed performance-based culture with strong accountability, pipeline hygiene, and cadence-based coaching across distributed teams. ● Launched and scaled BD/MD Agency Model across North America, reviving dormant SMB accounts and increasing rep ...
- Jul 06
San Jose, CA
... Languages: IBIS models, Verilog-A, HSpice, Python, Ocean scripting, TCL scripting, MATLAB, C, C++ Software: Cadence Virtuoso (ADE XL, Maestro, Layout XL), Ansys Totem, Ansys Helic, Matlab, Hspice, Cadence Allegro, JMP, Logisim, Avanwaves, Cosim ...
- Jul 06
Gilbert, AZ
... SunOS, Solaris, Windows XP, Macintosh OSX, AIX CAD Engineering Applications: TCAD, ICCAP, SPICE like simulators, ADS, ANSYS, Cadence, Synopsys, Mentor PROFESSIONAL EXPERIENCE Intel, Mesa, AZ (remote) Design Automation Engineer - Development Tools ...
- Jul 05
Cupertino, CA
... Performed simulations using HSPICE and Spectre, schematic capture, layout with Cadence Virtuoso (contractor), hardware testing. 1/00-4/03: National Semiconductor, Santa Clara, CA Design Engineer, worked on design of ESD circuits and CMOS I/O buffers ...
- Jul 04
Santa Clara, UT, 84765
... • Improved and streamlined product backlog for work deliverables with team, establishing regular delivery cadence on releases and working at 90% capacity. • Collaborated with internal and external stakeholders on the transition of 2.2M members from ...
- Jul 04
San Jose, CA
... ● Proficient in using Mentor Graphics/ Siemens and other EDA industry-standard tools for verification and Cadence, Synopsys electronic design automation tools. SKILLS: ● ● Neuromorphic processors Intel power/instruction optimization ● API, HPS, OS, ...
- Jul 04