| Resume alert | Resumes 41 - 50 of 508 |
Electrical Engineer
Fremont, CA
... languages and CAD tools proficiency Windows, Ubuntu, Visual C, Atmel IDE, MPLAB XIDE, GNU BASH and Python scripting Cadence Orcad, Altium Solidworks Modelsim (VHDL simulations) Vivado (VHDL, Verilog) Test equipment proficiency Scopes, logic ... - 2023 Jan 02
... languages and CAD tools proficiency Windows, Ubuntu, Visual C, Atmel IDE, MPLAB XIDE, GNU BASH and Python scripting Cadence Orcad, Altium Solidworks Modelsim (VHDL simulations) Vivado (VHDL, Verilog) Test equipment proficiency Scopes, logic ... - 2023 Jan 02
Business Development Account Manager
San Jose, CA
... Participate in forecast calls with partner sales management teams and cadence calls with internal/external sales teams. Act as a subject matter expert by on-boarding and training partners for pre-sales/sales/delivery services development Oversee all ... - 2022 Dec 25
... Participate in forecast calls with partner sales management teams and cadence calls with internal/external sales teams. Act as a subject matter expert by on-boarding and training partners for pre-sales/sales/delivery services development Oversee all ... - 2022 Dec 25
Sales Executive Account
Palo Alto, CA
... Team in the Silicon Valley featuring teammates of Google, Apple, Samsung, Facebook, Cadence, Cisco, Intel, HP, Microsoft, Journalists, Professors, tech professionals. Speech Communication – Santa Clara University Reference upon request KATIE NGUYEN - 2022 Jul 05
... Team in the Silicon Valley featuring teammates of Google, Apple, Samsung, Facebook, Cadence, Cisco, Intel, HP, Microsoft, Journalists, Professors, tech professionals. Speech Communication – Santa Clara University Reference upon request KATIE NGUYEN - 2022 Jul 05
Design Engineer Product
San Jose, CA
... with IC Design and test/evaluation skill can be utilized SUMMARY Hands-on experience in designing the High Speed PMIC, PLL, RT-OSC, DAC and many Analog & Mixed Signal Design using Cadence Toolset, Analog Artist, Spectre, HSPICE, and Verilog-XL. ... - 2022 Apr 29
... with IC Design and test/evaluation skill can be utilized SUMMARY Hands-on experience in designing the High Speed PMIC, PLL, RT-OSC, DAC and many Analog & Mixed Signal Design using Cadence Toolset, Analog Artist, Spectre, HSPICE, and Verilog-XL. ... - 2022 Apr 29
Sales Professional and Executive Assistant work.
Santa Clara, CA
... Worked on an internal project at Cadence Design Systems and moved an entire engineering department of 300 engineers and worked closely with a command center to coordinate the project. Worked effectively in start-ups and am flexible and adaptable to ... - 2021 Oct 04
... Worked on an internal project at Cadence Design Systems and moved an entire engineering department of 300 engineers and worked closely with a command center to coordinate the project. Worked effectively in start-ups and am flexible and adaptable to ... - 2021 Oct 04
Electrical Engineer Manufacturing
Campbell, CA
... Electronic Engineering Additional courses completed : Cadence Project Management, DFT, SJSU Microfabrication, JIT, TQC, PLC, Team Building, Time Management, Management and Leadership. 1998-1999 - 2021 Aug 12
... Electronic Engineering Additional courses completed : Cadence Project Management, DFT, SJSU Microfabrication, JIT, TQC, PLC, Team Building, Time Management, Management and Leadership. 1998-1999 - 2021 Aug 12
Hardware Engineer Engineering Technician
Fremont, CA
... Familiar with analog to digital converter circuit designing Using Mentor graphic (PAD), Allegro and Cadence for design, modeling and simulations Experience in schematic capture design or PCB layout Experience in creating footprint and library ... - 2021 Jul 02
... Familiar with analog to digital converter circuit designing Using Mentor graphic (PAD), Allegro and Cadence for design, modeling and simulations Experience in schematic capture design or PCB layout Experience in creating footprint and library ... - 2021 Jul 02
Digital and Physical Design Engineer, Verification Engineer
Santa Clara, CA
... and Telecommunication Engineering GPA: 9.12/10 TECHNICAL SKILLS Programming Languages: Verilog, SystemVerilog, Python Tools: Cadence Virtuoso, QuestaSim, Quartus, HSPICE, Xilinx Vivado, PrimeTime(STA), Innovus(PnR), Design Compiler(Synthesis) ... - 2021 May 30
... and Telecommunication Engineering GPA: 9.12/10 TECHNICAL SKILLS Programming Languages: Verilog, SystemVerilog, Python Tools: Cadence Virtuoso, QuestaSim, Quartus, HSPICE, Xilinx Vivado, PrimeTime(STA), Innovus(PnR), Design Compiler(Synthesis) ... - 2021 May 30
Engineering Manager Design Engineer
Los Gatos, CA, 95032
Djat/Leonard Bong ***** *** ***** ******* **, Los Gatos, CA 95032 Home: 408-***-**** Cell: 408-***-**** Email: admoi9@r.postjobfree.com Competency CAD automation flow for Cadence CAD tools and Synopsys CAD tools (20+ years) Unix/Linux system (25 ... - 2021 May 24
Djat/Leonard Bong ***** *** ***** ******* **, Los Gatos, CA 95032 Home: 408-***-**** Cell: 408-***-**** Email: admoi9@r.postjobfree.com Competency CAD automation flow for Cadence CAD tools and Synopsys CAD tools (20+ years) Unix/Linux system (25 ... - 2021 May 24
Network Security Engineer, VMWare NSX Engineer, Network Engineer
Hayward, CA
... GTM/LTM 2000, 5000, 6500, 6800 series, Cisco ACE 4710 Simulation Tools: Qualnet Developer, OPNET IT GURU, OPNET Modeler, Cadence Firewalls: Juniper net screen (500/5200), Juniper SRX (650/3600), Pix (525/535), ASA (5520/5550/5580 ), Checkpoint, ... - 2021 Mar 16
... GTM/LTM 2000, 5000, 6500, 6800 series, Cisco ACE 4710 Simulation Tools: Qualnet Developer, OPNET IT GURU, OPNET Modeler, Cadence Firewalls: Juniper net screen (500/5200), Juniper SRX (650/3600), Pix (525/535), ASA (5520/5550/5580 ), Checkpoint, ... - 2021 Mar 16